公开(公告)号：US07889570B2

公开(公告)日：2011-02-15

申请号：US11515799

申请日：2006-09-06

申请人： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

发明人： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

IPC分类号： G11C7/10

CPC分类号： G11C8/06 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/225

摘要： Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the input buffer is enabled only when the second signal shows a non-power down mode and the first signal shows a chip selection state. The input buffer is at least one selected from the group consisting of a row address strobe input buffer, a column address strobe input buffer, and an address input buffer.

摘要翻译： 提供了存储器件，存储器控制器和使用它的存储器系统的输入缓冲器。 响应于表示芯片选择信息的第一信号和表示掉电信息的第二信号，存储器件的输入缓冲器被使能或禁止，并且仅当第二信号显示非掉电模式时，输入缓冲器被使能，并且 第一信号显示芯片选择状态。 输入缓冲器是从由行地址选通输入缓冲器，列地址选通输入缓冲器和地址输入缓冲器组成的组中选择的至少一个。

公开(公告)号：US07042800B2

公开(公告)日：2006-05-09

申请号：US10951881

申请日：2004-09-29

申请人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

发明人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C29/46

摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

摘要翻译： 用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作 模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

公开(公告)号：US06643191B2

公开(公告)日：2003-11-04

申请号：US10102308

申请日：2002-03-19

申请人： Yun-sang Lee ,  Jong-hyun Choi ,  Sang-seok Kang

发明人： Yun-sang Lee ,  Jong-hyun Choi ,  Sang-seok Kang

IPC分类号： G11C700

CPC分类号： G11C29/44 ,  G11C8/12

摘要： A semiconductor memory device and a method of generating a chip selection signal that enable the analysis of the causes of defects of defective memory devices selected by a user from a system with a plurality of memory devices and the fixing the defects are provided. The semiconductor memory device includes a programming register, an input buffer control circuit, and a chip selection circuit. The programming register activates an output signal in response to an address and a command input from the outside. The input buffer control circuit activates the plurality of data input buffer circuits in response to the output signal of the programming register. The chip selection circuit activates a defect detecting & repairing circuit, such as a repair circuit or a test time shortening circuit, when at least one of output signals of the plurality of data input buffer circuits is in a first logic state.

公开(公告)号：US06404693B1

公开(公告)日：2002-06-11

申请号：US09634393

申请日：2000-08-09

申请人： Jong-hyun Choi ,  Dong-il Seo

发明人： Jong-hyun Choi ,  Dong-il Seo

IPC分类号： G11C800

CPC分类号： G11C7/1006 ,  G11C11/4087

摘要： Integrated circuit memory devices include a memory cell block that includes sub-array blocks and a first number of input/output line pairs adjacent each of a pair of opposing sides of each of the sub-array blocks. A circuit is configured to select one of the sub-array blocks and to input/output the first number of bits of data through the first number of input/output line pairs adjacent each of the pair of opposing sides of the selected one of the sub-array blocks. The circuit is further configured to select a second number of the sub-array blocks and to input/output the first number times the second number of bits of data through the first number of input/output line pairs adjacent each of a pair of opposing sides of the selected second number of the sub-array blocks. Accordingly, the number of input/output lines need not increase even when the bandwidth increases.

摘要翻译： 集成电路存储器件包括存储单元块，其包括子阵列块和与每个子阵列块的一对相对侧中的每一对相邻的第一数量的输入/输出线对。 电路被配置为选择子阵列块中的一个并且通过与子选择的一个子对中的每对相对侧相邻的第一数量的输入/输出线对来输入/输出第一数据位数 几何块。 电路还被配置为选择第二数量的子阵列块，并且通过与一对相对侧中的每一对相邻的第一数量的输入/输出线对来输入/输出第二数量的第二数量的位数 的所选择的第二数量的子阵列块。 因此，即使带宽增加，输入/输出线的数量也不需要增加。

公开(公告)号：US20070070782A1

公开(公告)日：2007-03-29

申请号：US11515799

申请日：2006-09-06

申请人： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

发明人： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

IPC分类号： G11C8/00

CPC分类号： G11C8/06 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/225

摘要： Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the input buffer is enabled only when the second signal shows a non-power down mode and the first signal shows a chip selection state. The input buffer is at least one selected from the group consisting of a row address strobe input buffer, a column address strobe input buffer, and an address input buffer.

摘要翻译： 提供了存储器件，存储器控制器和使用它的存储器系统的输入缓冲器。 响应于表示芯片选择信息的第一信号和表示掉电信息的第二信号，存储器件的输入缓冲器被使能或禁止，并且仅当第二信号显示非掉电模式时，输入缓冲器被使能，并且 第一信号显示芯片选择状态。 输入缓冲器是从由行地址选通输入缓冲器，列地址选通输入缓冲器和地址输入缓冲器组成的组中选择的至少一个。

公开(公告)号：US20050078548A1

公开(公告)日：2005-04-14

申请号：US10951881

申请日：2004-09-29

申请人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

发明人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/10 ,  G11C29/46

CPC分类号： G11C7/1045 ,  G11C29/46

摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

摘要翻译： 用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作 模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

公开(公告)号：US06661722B2

公开(公告)日：2003-12-09

申请号：US10190652

申请日：2002-07-08

申请人： Jae-young Lee ,  Jong-hyun Choi

发明人： Jae-young Lee ,  Jong-hyun Choi

IPC分类号： G11C700

CPC分类号： H01L27/0207 ,  G11C7/065

摘要： A bit line sense amplifier is provided. The bit line sense amplifier includes a first sense amplifier block in which a plurality of first sense amplifiers for sensing and amplifying data of a bit line or a complementary bit line are laid out, and first drivers, which are arranged outside the plurality of first sense amplifiers, for pulling down the bit line or the complementary bit line to a first voltage level. The bit line sense amplifier further includes a second sense amplifier block with a plurality of second sense amplifiers and second drivers for pulling up the bit line or the complementary bit line to a second voltage level. By arranging the drivers outside the bit sense amplifiers, effects caused by variation in critical dimensions (CDs) of gates are minimized and the entire area of the bit line sense amplifier is reduced.

摘要翻译： 提供位线读出放大器。 位线读出放大器包括第一读出放大器块，其中布置用于感测和放大位线或互补位线的数据的多个第一读出放大器，并且布置在多个第一感测之外的第一驱动器 放大器，用于将位线或互补位线拉低至第一电压电平。 位线读出放大器还包括具有多个第二读出放大器的第二读出放大器模块和用于将位线或互补位线提升到第二电压电平的第二驱动器。 通过将驱动器布置在位读出放大器之外，由栅极的关键尺寸（CD）的变化引起的影响被最小化，并且位线读出放大器的整个区域减小。

公开(公告)号：US06510096B2

公开(公告)日：2003-01-21

申请号：US09981945

申请日：2001-10-17

申请人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

发明人： Jong-hyun Choi ,  Jei-hwan Yoo ,  Jong-eon Lee ,  Hyun-soon Jang

IPC分类号： G11C802

CPC分类号： G11C5/143 ,  G11C7/22

摘要： A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

公开(公告)号：US5999471A

公开(公告)日：1999-12-07

申请号：US16831

申请日：1998-01-30

申请人： Jong-hyun Choi

发明人： Jong-hyun Choi

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A refresh method for a semiconductor memory device reduces the magnitude of the peak current drawn from the power supply. Multiple memory cells coupled to a plurality of word lines are refreshed at one time in order to reduce stand-by power consumption in the refresh mode. Such refresh mode can include automatic refresh or self refresh modes. A plurality of word lines are selected and multiple bit line sense amplifiers corresponding to the selected word lines are activated for the refresh operation. The selected plurality of bit line sense amplifiers are divided into two or more groups and the points in time at which the bit line sense amplifiers are enabled are different for each group. The selected word line and the selected bit line sense amplifiers are then disabled. Thus, the magnitude of the peak current is reduced by dispersing the points in time at which the bit line sense amplifiers are enabled, thereby preventing system misoperation by excessive peak currents in a battery powered system.

摘要翻译： 半导体存储器件的刷新方法减小了从电源抽取的峰值电流的大小。 耦合到多个字线的多个存储器单元一次刷新，以便减少刷新模式下的待机功耗。 这种刷新模式可以包括自动刷新或自刷新模式。 选择多个字线，并激活与所选择的字线对应的多个位线检测放大器进行刷新操作。 所选择的多个位线读出放大器被分成两组或更多组，并且位线读出放大器使能的时间点对于每个组是不同的。 然后禁用所选择的字线和所选位线读出放大器。 因此，通过分散位线读出放大器的时间点来减小峰值电流的大小，从而防止由电池供电的系统中的过大的峰值电流引起的系统误操作。

公开(公告)号：US5970325A

公开(公告)日：1999-10-19

申请号：US858974

申请日：1997-05-20

申请人： Jin Jang ,  Keun-soo Lee ,  Jong-hyun Choi

发明人： Jin Jang ,  Keun-soo Lee ,  Jong-hyun Choi

IPC分类号： H01L21/205 ,  H01L21/336 ,  H01L29/786 ,  H01L29/78

CPC分类号： H01L29/66765 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/78669

摘要： A thin-film switching device includes an active region including noncrystalline silicon, e.g., hydrogenated amorphous silicon, which includes chlorine distributed in a manner which produces a predetermined photoconductivity and a predetermined field-effect mobility in the active region. Preferably, the active region includes a plurality of hydrogenated amorphous silicon layers, at least one of which includes chlorine. In one embodiment, the plurality of hydrogenated amorphous silicon layers includes a hydrogenated amorphous silicon layer including between 0.1 ppm and 106 ppm chlorine. In another embodiment, the plurality of hydrogenated amorphous silicon layers includes a first hydrogenated amorphous silicon layer having a first chlorine concentration and a second hydrogenated amorphous silicon layer having a second chlorine concentration less than the first chlorine concentration. The first hydrogenated amorphous silicon layer includes 1 ppm to 105 ppm chlorine, and the second hydrogenated amorphous silicon layer includes less than 104 ppm chlorine. Related fabrication methods are also discussed.

摘要翻译： 薄膜开关器件包括包括非晶硅（例如氢化非晶硅）的有源区，其包括以有效区域中产生预定光电导率和预定场效应迁移率的方式分布的氯。 优选地，有源区包括多个氢化非晶硅层，其中至少一个包括氯。 在一个实施例中，多个氢化非晶硅层包括含0.1ppm至106ppm氯的氢化非晶硅层。 在另一实施例中，多个氢化非晶硅层包括具有第一氯浓度的第一氢化非晶硅层和具有小于第一氯浓度的第二氯浓度的第二氢化非晶硅层。 第一氢化非晶硅层包括1ppm至105ppm的氯，第二氢化非晶硅层包括小于104ppm的氯。 还讨论了相关的制造方法。