公开(公告)号：US07081662B1

公开(公告)日：2006-07-25

申请号：US11199833

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L29/00 ,  H01L29/73

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US08344416B2

公开(公告)日：2013-01-01

申请号：US12777672

申请日：2010-05-11

申请人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

发明人： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yu-Chang Jong ,  Chun-Chien Tsai

IPC分类号： H01L29/02

CPC分类号： H01L27/0251 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7835

摘要： An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

摘要翻译： 集成电路在衬底上包括至少一个晶体管。 第一保护环布置在至少一个晶体管周围。 第一保护环具有第一类型掺杂剂。 第二保护环设置在第一保护环周围。 第二保护环具有第二类型掺杂剂。 第一掺杂区域邻近第一保护环设置。 第一掺杂区具有第二类掺杂剂。 第二掺杂区域邻近第二保护环设置。 第二掺杂区具有第一类掺杂剂。 第一保护环，第二保护环，第一掺杂区和第二掺杂区能够用作第一可控硅整流器（SCR），以基本上释放静电放电（ESD）。

公开(公告)号：US20090294865A1

公开(公告)日：2009-12-03

申请号：US12127629

申请日：2008-05-27

申请人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

发明人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/872

摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。 含金属层和第一阱区形成肖特基势垒。 所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。 第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

公开(公告)号：US07384802B2

公开(公告)日：2008-06-10

申请号：US11438603

申请日：2006-05-22

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L21/00

CPC分类号： H01L27/0259

摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

摘要翻译： 提供一种静电放电（ESD）保护结构及其形成方法。 该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。 第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。 该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域， 第二高压井区域并物理接触场区域。 第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

公开(公告)号：US07372083B2

公开(公告)日：2008-05-13

申请号：US11199662

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L29/72

CPC分类号： H01L29/7393 ,  H01L27/0262 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7436

摘要： A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.

摘要翻译： 提供了具有静电放电（ESD）保护功能的高电压p型金属氧化物半导体（HVPMOS）器件及其形成方法。 HVPMOS包括PMOS晶体管，其中PMOS晶体管包括在高压p阱（HVPW）区域中掺杂有p型杂质的第一源极/漏极区域，掺杂有p型杂质的第二源极/漏极区域 在HVPW区域和HVNW区域彼此物理接触的场合，HVPW区域中基本上位于栅极电介质的场区域和第一重掺杂n型（N +）区域的高电压n阱（HVNW）区域中， 第一源极/漏极区域。 该器件还包括位于HVPW区域和HVNW区域下面的N +掩埋层和位于N +掩埋层下面的p型衬底。 该器件具有强大的正向和反向模式ESD性能。

公开(公告)号：US20080073745A1

公开(公告)日：2008-03-27

申请号：US11526419

申请日：2006-09-25

申请人： Chien-Shao Tang ,  Tsung-Yi Huang ,  David Ho ,  Zhe-Yi Wang ,  Yu-Chang Jong

发明人： Chien-Shao Tang ,  Tsung-Yi Huang ,  David Ho ,  Zhe-Yi Wang ,  Yu-Chang Jong

IPC分类号： H01L29/00

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： A high-voltage semiconductor structure includes a high-voltage well region overlying a substrate, an isolation region extending from a top surface of the high-voltage well region into the high-voltage well region, a low-voltage well region having at least a portion underlying and adjoining the isolation region wherein the low-voltage well region is inside of and of a same conductivity type as the high-voltage well region, a gate dielectric on the high-voltage well region, a gate electrode on the gate dielectric, and a source/drain region of the same conductivity type as the high-voltage well region, wherein the source/drain region is spaced apart from a channel region by the isolation region.

摘要翻译： 高电压半导体结构包括覆盖基板的高电压阱区域，从高压阱区域的顶表面延伸到高压阱区域的隔离区域，具有至少一个 隔离区域的底部和邻接部分，其中低电压阱区域在与高压阱区域相同的导电类型内，高电压阱区域上的栅极电介质，栅极电介质上的栅电极， 以及与高电压阱区相同导电类型的源/漏区，其中源极/漏极区通过隔离区与沟道区间隔开。

公开(公告)号：US06943062B2

公开(公告)日：2005-09-13

申请号：US10689430

申请日：2003-10-20

申请人： Hong-Miao Chen ,  Yu-Chang Jong ,  Huan-Chi Tseng

发明人： Hong-Miao Chen ,  Yu-Chang Jong ,  Huan-Chi Tseng

IPC分类号： B08B6/00 ,  B08B7/00 ,  C25F1/00 ,  C25F3/30 ,  C25F5/00 ,  F02D1/00 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： B08B7/0042 ,  H01L21/02046 ,  Y10S438/906

摘要： The invention describes how contaminant particles may be removed from a surface without in any way damaging that surface. First, the positional co-ordinates of all particles on the surface are recorded. Optionally, only particles that can be expected to cause current or future damage to the surface are included. Then, using optical tweezers, each particle is individually removed and then disposed of. Six different ways to remove and dispose of particles are described.

公开(公告)号：US06623911B1

公开(公告)日：2003-09-23

申请号：US09953524

申请日：2001-09-17

申请人： Yu-Chang Jong ,  Tai-Yuan Wu

发明人： Yu-Chang Jong ,  Tai-Yuan Wu

IPC分类号： G03F720

CPC分类号： H01L23/544 ,  G03F7/203 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a clear code mark that is independent of backend planarization by adding an extra exposing step to the normal photolithography process is described. A layer to be patterned is provided on a substrate. A photoresist layer is coated overlying the layer to be patterned. The photoresist layer is first exposed through a code mask and second exposed through a patterning mask. The photoresist layer is developed to form a photoresist mask having a code mark pattern from the code mask and a device pattern from the patterning mask. The layer to be patterned is etched away where it is not covered by the photoresist mask to form simultaneously device structures and a code mark in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过向普通光刻工艺添加额外的暴露步骤来形成独立于后端平面化的清晰代码标记的方法。 待图案化的层设置在基板上。 将光致抗蚀剂层涂覆在待图案化的层上。 光致抗蚀剂层首先通过代码掩模曝光，并通过图案掩模曝光。 显影光致抗蚀剂层以形成具有来自编码掩模的码标图案和来自图案化掩模的器件图案的光致抗蚀剂掩模。 要被图案化的层被蚀刻掉，其不被光致抗蚀剂掩模覆盖，以在集成电路器件的制造中同时形成器件结构和代码标记。

公开(公告)号：US08324705B2

公开(公告)日：2012-12-04

申请号：US12127629

申请日：2008-05-27

申请人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

发明人： Chien-Shao Tang ,  Dah-Chuen Ho ,  Yu-Chang Jong ,  Zhe-Yi Wang ,  Yuh-Hwa Chang ,  Yogendra Yadav

IPC分类号： H01L29/872

CPC分类号： H01L27/0629 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/872

摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。 含金属层和第一阱区形成肖特基势垒。 所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。 第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

公开(公告)号：US20050081824A1

公开(公告)日：2005-04-21

申请号：US10689430

申请日：2003-10-20

申请人： Hong-Miao Chen ,  Yu-Chang Jong ,  Huan-Chi Tseng

发明人： Hong-Miao Chen ,  Yu-Chang Jong ,  Huan-Chi Tseng

IPC分类号： B08B6/00 ,  B08B7/00 ,  C25F1/00 ,  C25F3/30 ,  C25F5/00 ,  F02D1/00 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： B08B7/0042 ,  H01L21/02046 ,  Y10S438/906

摘要： The invention describes how contaminant particles may be removed from a surface without in any way damaging that surface. First, the positional co-ordinates of all particles on the surface are recorded. Optionally, only particles that can be expected to cause current or future damage to the surface are included. Then, using optical tweezers, each particle is individually removed and then disposed of. Six different ways to remove and dispose of particles are described.

摘要翻译： 本发明描述了如何从表面去除污染物颗粒，而不会以任何方式损坏该表面。 首先，记录表面上所有颗粒的位置坐标。 可选地，仅包括可以预期会对表面造成当前或未来损害的颗粒。 然后，使用光学镊子，分别除去每个颗粒，然后处理。 描述了去除和处理颗粒的六种不同的方法。