公开(公告)号：US08362454B2

公开(公告)日：2013-01-29

申请号：US12334203

申请日：2008-12-12

申请人： Hengyuan Lee ,  Pang-Hsu Chen ,  Tai-Yuan Wu ,  Ching-Chiun Wang

发明人： Hengyuan Lee ,  Pang-Hsu Chen ,  Tai-Yuan Wu ,  Ching-Chiun Wang

IPC分类号： H01L27/24

CPC分类号： H01L45/1641 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1658

摘要： A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode is formed on the oxygen atom gettering layer. The previous mentioned structure is subjected to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, thus leaving a plurality of oxygen vacancies of the metal oxide layer.

摘要翻译： 提供了一种电阻随机存取存储器及其制造方法。 该方法包括提供形成在基板上的底部电极。 在底部电极上形成金属氧化物层。 在金属氧化物层上形成氧原子吸气层。 在氧原子吸气层上形成顶部电极。 对前述结构进行热处理，驱动金属氧化物层的氧原子迁移到氧原子吸气层中并与氧原子吸气层反应，从而留下金属氧化物层的多个氧空位。

公开(公告)号：US20100164062A1

公开(公告)日：2010-07-01

申请号：US12480694

申请日：2009-06-09

申请人： Ching-Chiun Wang ,  Tai-Yuan Wu ,  Yu-Sheng Chen ,  Cha-Hsin Lin

发明人： Ching-Chiun Wang ,  Tai-Yuan Wu ,  Yu-Sheng Chen ,  Cha-Hsin Lin

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/90 ,  H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L27/0629 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/013

摘要： A method of manufacturing through-silicon-via (TSV) and a TSV structure are provided. The TSV structure includes a silicon substrate, an annular capacitor, a conductive through-via, a layer of low-k material, and a bump. The annular capacitor is within the silicon substrate and constituted of a first conductive layer, a capacitor dielectric layer, and a second conductive layer from the inside to the outside. The conductive through-via is disposed in the silicon substrate surrounded by the annular capacitor, and the layer of low-k material is between the annular capacitor and the conductive through-via. The bump is in touch with the conductive through-via for bonding other chip.

摘要翻译： 提供了通过硅通孔（TSV）和TSV结构的方法。 TSV结构包括硅衬底，环形电容器，导电通孔，低k材料层和凸块。 环形电容器在硅衬底内，由第一导电层，电容器电介质层和从内向外的第二导电层构成。 导电通孔设置在由环形电容器包围的硅衬底中，低k材料层位于环形电容器和导电通孔之间。 凸块与用于粘合其他芯片的导电通孔相接触。

公开(公告)号：US20100038791A1

公开(公告)日：2010-02-18

申请号：US12334203

申请日：2008-12-12

申请人： Hengyuan Lee ,  Pang-Hsu Chen ,  Tai-Yuan Wu ,  Ching-Chiun Wang

发明人： Hengyuan Lee ,  Pang-Hsu Chen ,  Tai-Yuan Wu ,  Ching-Chiun Wang

IPC分类号： H01L29/45 ,  H01L21/44

CPC分类号： H01L45/1641 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1658

摘要： A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode is formed on the oxygen atom gettering layer. The previous mentioned structure is subjected to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, thus leaving a plurality of oxygen vacancies of the metal oxide layer.

摘要翻译： 提供了一种电阻随机存取存储器及其制造方法。 该方法包括提供形成在基板上的底部电极。 在底部电极上形成金属氧化物层。 在金属氧化物层上形成氧原子吸气层。 在氧原子吸气层上形成顶部电极。 对前述结构进行热处理，驱动金属氧化物层的氧原子迁移到氧原子吸气层中并与氧原子吸气层反应，从而留下金属氧化物层的多个氧空位。

公开(公告)号：US20130320289A1

公开(公告)日：2013-12-05

申请号：US13612844

申请日：2012-09-13

申请人： Wei-Su Chen ,  Tai-Yuan Wu ,  Frederick T. Chen ,  Pang-Hsu Chen

发明人： Wei-Su Chen ,  Tai-Yuan Wu ,  Frederick T. Chen ,  Pang-Hsu Chen

IPC分类号： H01L45/00

CPC分类号： H01L45/145 ,  H01L45/08 ,  H01L45/1608 ,  H01L45/1675

摘要： A resistance random access memory including a first electrode layer, a second electrode layer, and a stacked structure is provided. The stacked structure includes a HfZrON layer and a ZrON layer and is located between the first electrode layer and the second electrode layer. In addition, the disclosure further provides a method of fabricating a resistance random access memory.

摘要翻译： 提供包括第一电极层，第二电极层和堆叠结构的电阻随机存取存储器。 堆叠结构包括HfZrON层和ZrON层，并且位于第一电极层和第二电极层之间。 另外，本发明还提供一种制造电阻随机存取存储器的方法。

公开(公告)号：US20090114899A1

公开(公告)日：2009-05-07

申请号：US12141966

申请日：2008-06-19

申请人： HENG-YUAN LEE ,  CHING-CHIUN WANG ,  PANG-HSU CHEN ,  TAI-YUAN WU

发明人： HENG-YUAN LEE ,  CHING-CHIUN WANG ,  PANG-HSU CHEN ,  TAI-YUAN WU

IPC分类号： H01L47/00 ,  H01L21/8234

CPC分类号： H01L27/101 ,  H01L45/04 ,  H01L45/145

摘要： A resistance memory is manufactured using semiconductor processing to comprise planar dual-tip electrodes so that the electric field in the resistance memory is concentrated to reduce the number of fuses in the dielectric material and improve the device characteristics. The resistance memory comprises: a first memory cell including a first bottom electrode and a common top electrode; and a second memory cell including a second bottom electrode and the common top electrode shared with the first memory cell; wherein the first bottom electrode, the second bottom electrode and the common top electrode are disposed on the same plane and are separated by a resistive conversion layer; wherein the common top electrode is connected to the ground through a via, while the first bottom electrode and the second bottom electrode are connected to the source of a transistor through a plug, respectively.

摘要翻译： 使用半导体处理制造电阻存​​储器以包括平面双尖端电极，使得电阻存储器中的电场集中以减少电介质材料中的熔丝数量并提高器件特性。 电阻存储器包括：第一存储单元，包括第一底电极和公共顶电极; 以及第二存储单元，包括与第一存储单元共用的第二底电极和公共顶电极; 其中所述第一底部电极，所述第二底部电极和所述公共顶部电极设置在同一平面上并由电阻转换层分离; 其中公共顶部电极通过通孔连接到地面，而第一底部电极和第二底部电极分别通过插头连接到晶体管的源极。

公开(公告)号：US06623911B1

公开(公告)日：2003-09-23

申请号：US09953524

申请日：2001-09-17

申请人： Yu-Chang Jong ,  Tai-Yuan Wu

发明人： Yu-Chang Jong ,  Tai-Yuan Wu

IPC分类号： G03F720

CPC分类号： H01L23/544 ,  G03F7/203 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a clear code mark that is independent of backend planarization by adding an extra exposing step to the normal photolithography process is described. A layer to be patterned is provided on a substrate. A photoresist layer is coated overlying the layer to be patterned. The photoresist layer is first exposed through a code mask and second exposed through a patterning mask. The photoresist layer is developed to form a photoresist mask having a code mark pattern from the code mask and a device pattern from the patterning mask. The layer to be patterned is etched away where it is not covered by the photoresist mask to form simultaneously device structures and a code mark in the fabrication of an integrated circuit device.

摘要翻译： 描述了通过向普通光刻工艺添加额外的暴露步骤来形成独立于后端平面化的清晰代码标记的方法。 待图案化的层设置在基板上。 将光致抗蚀剂层涂覆在待图案化的层上。 光致抗蚀剂层首先通过代码掩模曝光，并通过图案掩模曝光。 显影光致抗蚀剂层以形成具有来自编码掩模的码标图案和来自图案化掩模的器件图案的光致抗蚀剂掩模。 要被图案化的层被蚀刻掉，其不被光致抗蚀剂掩模覆盖，以在集成电路器件的制造中同时形成器件结构和代码标记。

公开(公告)号：US20090191685A1

公开(公告)日：2009-07-30

申请号：US12179996

申请日：2008-07-25

申请人： Heng-Yuan LEE ,  Ching-Chiun WANG ,  Tai-Yuan WU

发明人： Heng-Yuan LEE ,  Ching-Chiun WANG ,  Tai-Yuan WU

IPC分类号： H01L21/334

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855

摘要： A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer to cover the second insulating layer, a sidewall portion of the mold cavity, the second plug and the etching stop layer; removing the second insulating layer so that the first electrode layer forms a single open-ended cavity; and depositing a dielectric layer and a second electrode layer.

摘要翻译： 一种用于在动态随机存取存储器中形成电容器的方法，包括以下步骤：提供至少具有晶体管的半导体衬底，其中形成至少具有第一插塞的层间介电层，使得第一插头连接到漏极 的晶体管; 在所述第一插塞和所述层间电介质层上沉积蚀刻停止层; 在所述蚀刻停止层上沉积第一绝缘层; 在所述第一绝缘层和所述蚀刻停止层上形成至少第二插头，使得所述第二插头连接到所述第一插头; 在第一绝缘层和第二插塞上沉积第二绝缘层; 在所述第二绝缘层中至少形成模腔，使得所述模腔的孔径大于所述第二插塞的直径，并且所述模腔和所述第二插塞之间存在偏差; 去除模腔中的第一绝缘层直到蚀刻停止层; 沉积第一电极层以覆盖第二绝缘层，模腔的侧壁部分，第二插塞和蚀刻停止层; 去除第二绝缘层，使得第一电极层形成单个开口腔; 以及沉积介电层和第二电极层。

公开(公告)号：US06531374B2

公开(公告)日：2003-03-11

申请号：US09927958

申请日：2001-08-10

申请人： Kun-I Lee ,  Tai-Yuan Wu ,  Ren-Jyh Leu ,  Hung-Chih Chen

发明人： Kun-I Lee ,  Tai-Yuan Wu ,  Ren-Jyh Leu ,  Hung-Chih Chen

IPC分类号： H01L2176

CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Correction of overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited, is disclosed. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.

摘要翻译： 公开了沉积在半导体晶片上的外延硅层和随后沉积的后外延硅层的覆盖偏移的校正。 当沉积给定厚度的外延硅层时，用于沉积的零标记坐标相对于晶片上的对准标记基于层的厚度移动一定距离。 距离优选与外延层的厚度成比例。 这防止了外延层的覆盖移位。 对于随后沉积的后外延硅层，优选除了第一后外延层之外，最初执行清除工艺以保持半导体晶片上的对准标记。 这样就可以防止后外延层的覆盖偏移或未对准。

公开(公告)号：US20140077149A1

公开(公告)日：2014-03-20

申请号：US13615683

申请日：2012-09-14

申请人： Frederick T. Chen ,  Heng-Yuan Lee ,  Yu-Sheng Chen ,  Wei-Su Chen ,  Tai-Yuan Wu ,  Pang-Hsu Chen

发明人： Frederick T. Chen ,  Heng-Yuan Lee ,  Yu-Sheng Chen ,  Wei-Su Chen ,  Tai-Yuan Wu ,  Pang-Hsu Chen

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： G11C13/0007 ,  G11C2213/15 ,  G11C2213/56 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146

摘要： A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are comparably mobile in each of the dominant resistance layer(s) and the auxiliary resistance layer(s), and the maximum resistance of the at least one dominant resistance layer is higher than that of the at least one auxiliary resistance layer.

摘要翻译： 提供了包括可变电阻层的电阻存储单元。 可变电阻层包括至少一个显性电阻层和至少一个辅助电阻层。 主要电阻层和辅助电阻层总体上形成封闭的离子交换系统，交换的离子在每个主要电阻层和辅助电阻层中是可比较的，以及 至少一个主要电阻层的最大电阻高于至少一个辅助电阻层的最大电阻。

公开(公告)号：US07799653B2

公开(公告)日：2010-09-21

申请号：US12179996

申请日：2008-07-25

申请人： Heng-Yuan Lee ,  Ching-Chiun Wang ,  Tai-Yuan Wu

发明人： Heng-Yuan Lee ,  Ching-Chiun Wang ,  Tai-Yuan Wu

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855

摘要： A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer to cover the second insulating layer, a sidewall portion of the mold cavity, the second plug and the etching stop layer; removing the second insulating layer so that the first electrode layer forms a single open-ended cavity; and depositing a dielectric layer and a second electrode layer.

摘要翻译： 一种用于在动态随机存取存储器中形成电容器的方法，包括以下步骤：提供至少具有晶体管的半导体衬底，其中形成至少具有第一插塞的层间介电层，使得第一插头连接到漏极 的晶体管; 在所述第一插塞和所述层间电介质层上沉积蚀刻停止层; 在所述蚀刻停止层上沉积第一绝缘层; 在所述第一绝缘层和所述蚀刻停止层上形成至少第二插头，使得所述第二插头连接到所述第一插头; 在第一绝缘层和第二插塞上沉积第二绝缘层; 在所述第二绝缘层中至少形成模腔，使得所述模腔的孔径大于所述第二插塞的直径，并且所述模腔和所述第二插塞之间存在偏差; 去除模腔中的第一绝缘层直到蚀刻停止层; 沉积第一电极层以覆盖第二绝缘层，模腔的侧壁部分，第二插塞和蚀刻停止层; 去除第二绝缘层，使得第一电极层形成单个开口腔; 以及沉积介电层和第二电极层。