公开(公告)号：US20050253249A1

公开(公告)日：2005-11-17

申请号：US11131084

申请日：2005-05-17

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: G02F1/1362 ,  H01L21/302 ,  H01L21/31 ,  H01L21/461 ,  H01L21/469 ,  H01L21/8242 ,  H01L23/053 ,  H01L23/12 ,  H01L23/522

CPC classification number: H01L23/5221 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

Abstract translation: 一种多层导线结构，包括：基板，形成在第一层上的多个第一导电线，该第一导电线在基板上沿着第一方向彼此平行地延伸;多个第二导电线，形成在第一层上的第一层 在与第一方向正交的第二方向上彼此平行地延伸的多个第三导线组，所述第二导电线形成在第一方向上延伸，每组第三导线对应于第一导线之一， 以及形成在所述第一层和所述第二层之间的多组导电路径，每组导电路径对应于所述第一导电线中的一条和一组第三导电线，并将相应的第一导电线电连接到相应的集合 的第三导线。

公开(公告)号：US07960731B2

公开(公告)日：2011-06-14

申请号：US11870426

申请日：2007-10-11

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen ,  Chi-Ming Chang

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen ,  Chi-Ming Chang

IPC: H01L21/84

CPC classification number: H01L27/1288 ,  G02F1/1368 ,  H01L27/124

Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.

Abstract translation: 提供多层互补导电线结构，其制造方法和TFT（薄膜晶体管）显示阵列的制造方法。 具有多层互补导电线结构的TFT的工艺与当前工艺相比不需要增加掩模数，并且能够解决显示器内部的线的电阻问题。

公开(公告)号：US07435667B2

公开(公告)日：2008-10-14

申请号：US10772511

申请日：2004-02-05

Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Yih-Rong Luo

Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Yih-Rong Luo

IPC: H01L21/20

CPC classification number: H01L21/02686 ,  C30B13/24 ,  C30B29/06 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78603

Abstract: A heat sink layer is formed on portions of a substrate, and then an amorphous silicon layer is formed thereon. The heat coefficient of the sink layer is greater than that of the substrate. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer on the heat sink layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer on the substrate to form polysilicon having a crystal size of a micrometer.

Abstract translation: 在衬底的部分上形成散热层，然后在其上形成非晶硅层。 吸收层的热系数大于衬底的热系数。 当准分子激光器加热非晶硅层以使非晶硅结晶时，在散热层上的非晶硅层中形成成核位点。 接着，在基板上的非晶硅层发生横向膨胀结晶，形成晶体尺寸为微米的多晶硅。

公开(公告)号：US20080108195A1

公开(公告)日：2008-05-08

申请号：US11963854

申请日：2007-12-24

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L21/336

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

公开(公告)号：US07339190B2

公开(公告)日：2008-03-04

申请号：US11308710

申请日：2006-04-25

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L29/76

CPC classification number: H01L29/78696 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/12 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/4234 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/78675 ,  H01L29/792

Abstract: A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Abstract translation: 提供了适于布置在基板上的存储单元。 存储单元包括多晶硅岛，第一介电层，俘获层，第二介质层和控制栅极。 多硅岛设置在衬底上，并且包括源极区，漏极区和位于源极和漏极区之间的沟道区。 通道区域在其上具有多个规则排列的尖端。 第一介电层设置在多晶硅岛上。 捕获层设置在第一介电层上。 第二介质层设置在捕获层上。 控制栅极设置在第二电介质层上。 上述存储单元可以集成到LTPS-LCD面板或OLED面板中。

公开(公告)号：US20070085115A1

公开(公告)日：2007-04-19

申请号：US11308612

申请日：2006-04-12

Applicant: Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Chi-Wen Chen ,  Ting-Chang Chang

Inventor： Hung-Tse Chen ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Chi-Wen Chen ,  Ting-Chang Chang

IPC: H01L31/113 ,  H01L31/062 ,  H01L21/84 ,  H01L21/00

CPC classification number: H01L27/1214 ,  H01L29/40117 ,  H01L29/66833

Abstract: A memory cell, suitable for being disposed on a substrate, comprises a poly-Si island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-Si island is disposed on the substrate and includes a source doped region, a drain doped region and a channel region there-between. The first dielectric layer is disposed on the poly-Si island, the trapping layer is disposed on the first dielectric layer, the second dielectric layer is disposed on the trapping layer and the control gate is disposed on the second dielectric layer. The above-described memory cell can be integrated into the manufacturing process of a low temperature polysilicon LCD panel (LTPS LCD panel) or an organic light emitting display panel (OLED panel).

Abstract translation: 适用于设置在基板上的存储单元包括多晶硅岛，第一介电层，俘获层，第二介电层和控制栅。 多晶硅岛设置在衬底上，包括源极掺杂区，漏极掺杂区和其间的沟道区。 第一介电层设置在多晶硅岛上，俘获层设置在第一介电层上，第二介电层设置在俘获层上，控制栅设置在第二介质层上。 上述存储单元可以集成到低温多晶硅LCD面板（LTPS LCD面板）或有机发光显示面板（OLED面板）的制造过程中。

公开(公告)号：US07161226B2

公开(公告)日：2007-01-09

申请号：US11131084

申请日：2005-05-17

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: H01L29/00

CPC classification number: H01L23/5221 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

Abstract translation: 一种多层导线结构，包括：基板，形成在第一层上的多个第一导电线，该第一导电线在基板上沿着第一方向彼此平行地延伸;多个第二导电线，形成在第一层上的第一层 在与第一方向正交的第二方向上彼此平行地延伸的多个第三导线组，所述第二导电线形成在第一方向上延伸，每组第三导线对应于第一导线之一， 以及形成在所述第一层和所述第二层之间的多组导电路径，每组导电路径对应于所述第一导电线中的一条和一组第三导电线，并将相应的第一导电线电连接到相应的集合 的第三导线。

公开(公告)号：US20060172469A1

公开(公告)日：2006-08-03

申请号：US11312473

申请日：2005-12-21

Applicant: Jia-Xing Lin ,  Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Jia-Xing Lin ,  Yu-Cheng Chen ,  Chi-Lin Chen

IPC: H01L21/84 ,  H01L21/20

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

Abstract: An amorphous silicon (a-Si) layer is first formed on a substrate, and the a-Si layer is next patterned to form silicon islands for defining device active regions. Then, a single shot laser beam with long pulse is utilized to irradiate each silicon island, and lateral growth crystallization is induced in each silicon island for transforming a-Si into polycrystalline silicon (poly-Si). Finally, the general subsequent processes for thin film transistor (TFT) fabrication are performed in turn to fabricate poly-Si TFTs.

Abstract translation: 首先在衬底上形成非晶硅（a-Si）层，然后将a-Si层图案化以形成用于限定器件有源区的硅岛。 然后，利用具有长脉冲的单次激光束照射每个硅岛，并且在每个硅岛中诱导横向生长结晶以将a-Si转化为多晶硅（poly-Si）。 最后，依次进行薄膜晶体管（TFT）制造的一般后续处理以制造多晶硅TFT。

公开(公告)号：US20060088986A1

公开(公告)日：2006-04-27

申请号：US11222804

申请日：2005-09-12

Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Po-Hao Tsai

Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Po-Hao Tsai

IPC: H01L21/20

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1281 ,  H01L29/66757

Abstract: An amorphous silicon layer and at least a heat-retaining layer are formed on a substrate in turn. Wherein, the heat-retaining layer is controlled to have an anti-reflective thickness for reducing the threshold laser energy to effect the melting of the amorphous silicon layer. Then, a laser irradiation process is performed to transform the amorphous silicon layer into a polycrystalline silicon layer. During the laser irratiation process, a portion of the laser energy transmits the heat-retaining layer to effect the melting of the amorphous silicon layer, and another portion of the laser energy is absorbed by the heat-retaining layer.

Abstract translation: 依次在基板上形成非晶硅层和至少一个保温层。 其中，保温层被控制为具有用于降低阈值激光能量以实现非晶硅层熔化的抗反射厚度。 然后，执行激光照射处理以将非晶硅层转变成多晶硅层。 在激光照射过程中，激光能量的一部分透过保温层来实现非晶硅层的熔化，另一部分激光能被保温层吸收。

公开(公告)号：US20060043072A1

公开(公告)日：2006-03-02

申请号：US11194314

申请日：2005-08-01

Applicant: Yu-Cheng Chen ,  Jia-Xing Lin ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Jia-Xing Lin ,  Chi-Lin Chen

IPC: C03C15/00

CPC classification number: H01L21/02675 ,  C03C15/00 ,  C03C15/02 ,  C03C23/0025 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L21/32115 ,  H01L29/6675 ,  H01L29/78606

Abstract: A method for planarizing polysilicon comprises providing a substrate, forming a dielectric layer on the substrate, forming an amorphous silicon film on the dielectric layer, etching the amorphous silicon film to remove native oxide formed on a surface of the amorphous silicon film, exposing the surface of the amorphous silicon film to a first radiation source to polycrystallize the amorphous silicon film into a polysilicon film, etching the polysilicon film to remove weak bonded silicon formed on a surface of the polysilicon film, and exposing the surface of the polysilicon film to a second radiation source to reflow the polysilicon film.

Abstract translation: 一种用于平坦化多晶硅的方法包括：提供衬底，在衬底上形成电介质层，在电介质层上形成非晶硅膜，蚀刻非晶硅膜以去除在非晶硅膜的表面上形成的自然氧化物， 将所述非晶硅膜施加到第一辐射源以将所述非晶硅膜多晶化为多晶硅膜，蚀刻所述多晶硅膜以去除在所述多晶硅膜的表面上形成的弱键合硅，并将所述多晶硅膜的表面暴露于第二 辐射源来回流多晶硅膜。