公开(公告)号：US08513079B2

公开(公告)日：2013-08-20

申请号：US12259144

申请日：2008-10-27

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/517 ,  H01L29/66757 ,  H01L29/66833 ,  H01L29/792

摘要： A device having thin-film transistor (TFT) silicon-aluminum oxide-silicon (SAS) memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface, an aluminum oxide layer overlying the P− polysilicon layer; and at least one control gate overlying the aluminum oxide layer. In a specific embodiment, the control gate is made of highly doped P+ polysilicon. A method for making the TFT SAS memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

摘要翻译： 提供一种具有薄膜晶体管（TFT）硅 - 氧化铝 - 硅（SAS）存储单元结构的器件。 该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。 介电层与第一表面相关联。 所述一个或多个源区或漏区中的每一个包括在导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。 另外，该器件包括覆盖共面表面的P-多晶硅层，覆盖在P-多晶硅层上的氧化铝层; 以及覆盖氧化铝层的至少一个控制栅极。 在具体实施例中，控制栅由高掺杂P +多晶硅制成。 提供了用于制造TFT SAS存储单元结构的方法，并且可以重复三维地集成结构。

公开(公告)号：US08415218B2

公开(公告)日：2013-04-09

申请号：US12259128

申请日：2008-10-27

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/336 ,  H01L21/20 ,  H01L21/36 ,  H01L21/00 ,  C23C16/24 ,  H01L29/06 ,  H01L47/02 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/80 ,  H01L29/76 ,  H01L29/788 ,  H01L21/70

CPC分类号： H01L21/02381 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/78672

摘要： A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.

摘要翻译： 提供了生长外延硅层的方法。 该方法包括提供包含氧封端的硅表面的衬底，并在氧封端的硅表面上形成第一个氢封端的硅表面。 此外，该方法包括通过原子层沉积（ALD）外延从由Ar流和闪光灯退火辅助的SiH 4热裂解基团连续形成在第一氢封端硅表面上的第二氢封端硅表面。 第二个氢封端的硅表面能够连续地由Ar流和闪光灯退火辅助的SiH 4热裂解基团通过ALD外延添加一层或多层硅。 在一个实施例中，该方法被应用于制造具有能够进行三维集成的薄膜晶体管（TFT）浮动栅极存储单元结构的器件。

公开(公告)号：US08105920B2

公开(公告)日：2012-01-31

申请号：US12259015

申请日：2008-10-27

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/00

CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L27/12 ,  H01L29/8616

摘要： A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.

摘要翻译： 具有非晶硅（a-Si）金属 - 氧化铝半导体（MAS）存储单元结构的半导体器件。 该器件包括衬底，覆盖在衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域，其中n型a-Si的共面表面和电介质层。 另外，器件包括p-i-n a-Si二极管结。 该器件还包括在a-Si p-i-n二极管结上的氧化铝电荷俘获层和覆盖氧化铝层的金属控制栅极。 提供了一种用于制造a-Si MAS存储单元结构并且可以重复三维地集成结构的方法。

公开(公告)号：US20110065281A1

公开(公告)日：2011-03-17

申请号：US12869620

申请日：2010-08-26

申请人： DAVID GAO ,  Fumitake Mieno

发明人： DAVID GAO ,  Fumitake Mieno

IPC分类号： H01L21/306

CPC分类号： H01L21/02057 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： A method for fabricating semiconductor devices includes providing a semiconductor substrate having a surface region containing one or more contaminants and having an overlying oxide layer. In an embodiment, the one or more contaminants are at least a carbon species. The method includes processing the surface region using at least a wet processing process to selectively remove the overlying oxide layer and expose the surface region including the one or more contaminants. The method includes subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 1 second to increase a temperature of the surface region to greater than 1000 degrees Celsius to remove the one or more contaminants. The method includes removing the high energy electromagnetic radiation to cause a reduction in temperature to about 300 to about 600 degrees Celsius in a time period of less than 1 second.

摘要翻译： 一种制造半导体器件的方法包括提供具有包含一种或多种污染物并具有上覆氧化物层的表面区域的半导体衬底。 在一个实施方案中，一种或多种污染物是至少一种碳物质。 该方法包括使用至少湿法处理工艺来处理表面区域，以选择性地去除上覆的氧化物层并暴露包括一种或多种污染物的表面区域。 该方法包括使表面区域经受约300至约800纳米的波长范围为小于1秒的高能电磁辐射，以将表面区域的温度升高到大于1000摄氏度，以除去一个 或更多的污染物。 该方法包括去除高能量电磁辐射，以在小于1秒的时间段内将温度降低到约300至约600摄氏度。

公开(公告)号：US07709386B2

公开(公告)日：2010-05-04

申请号：US12141045

申请日：2008-06-17

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L21/44

CPC分类号： H01L21/0228 ,  C23C16/45529 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/11563

摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within the ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; and forming a second discrete compound monolayer above the semiconductor substrate by the same process as that for forming the first discrete compound monolayer. There is also provided a semiconductor device in which the charge trapping layer is a dielectric layer containing the first and second discrete compound monolayers formed by the ALD method.

摘要翻译： 提供了一种制造半导体器件的方法，包括以下步骤：将第一前体气体流到ALD室内的半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 以及通过与形成第一离散化合物单层相同的方法在半导体衬底上方形成第二离散化合物单层。 还提供了一种半导体器件，其中电荷捕获层是包含通过ALD法形成的第一和第二离散化合物单层的介电层。

公开(公告)号：US20100009528A1

公开(公告)日：2010-01-14

申请号：US12259095

申请日：2008-10-27

申请人： David GAO ,  Fumitake Mieno

发明人： David GAO ,  Fumitake Mieno

IPC分类号： H01L21/28 ,  H01L21/31

CPC分类号： H01L21/31654 ,  H01L21/02233 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/28211 ,  H01L21/28282

摘要： A method for fabricating semiconductor devices, e.g., SONOS cell. The method includes providing a semiconductor substrate (e.g., silicon wafer, silicon on insulator) having a surface region, which has a native oxide layer. The method includes treating the surface region to a wet cleaning process to remove a native oxide layer from the surface region. In a specific embodiment, the method includes subjecting the surface region to an oxygen bearing environment and subjecting the surface region to a high energy electromagnetic radiation having wavelengths ranging from about 300 to about 800 nanometers for a time period of less than 10 milli-seconds to increase a temperature of the surface region to greater than 1000 Degrees Celsius. In a specific embodiment, the method causes formation of an oxide layer having a thickness of less than 10 Angstroms. In a preferred embodiment, the oxide layer is substantially free from pinholes and other imperfections. In a specific embodiment, the oxide layer is a gate oxide layer.

摘要翻译： 一种制造半导体器件的方法，例如SONOS电池。 该方法包括提供具有自然氧化物层的具有表面区域的半导体衬底（例如，硅晶片，绝缘体上硅）。 该方法包括将表面区域处理为湿清洗工艺以从表面区域去除自然氧化物层。 在一个具体实施方案中，该方法包括使表面区域承受含氧环境，并使表面区域经受波长为约300至约800纳米的高能电磁辐射，持续时间小于10毫秒至 将表面区域的温度增加到大于1000摄氏度。 在一个具体实施方案中，该方法导致形成厚度小于10埃的氧化物层。 在优选实施例中，氧化物层基本上没有针孔和其它缺陷。 在具体实施方案中，氧化物层是栅极氧化物层。

公开(公告)号：US06300217B1

公开(公告)日：2001-10-09

申请号：US09069170

申请日：1998-04-29

申请人： Masaki Kuramae ,  Fumitake Mieno

发明人： Masaki Kuramae ,  Fumitake Mieno

IPC分类号： H01L2120

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L28/84 ,  H01L28/87 ,  Y10S438/901

摘要： A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在衬底上沉积非晶硅层，并通过用氧化气体处理非晶硅层的表面，在非晶硅层的表面上形成氧化膜。 形成步骤在非晶硅层结晶之前发生。

公开(公告)号：US09478654B2

公开(公告)日：2016-10-25

申请号：US13369782

申请日：2012-02-09

申请人： Fumitake Mieno ,  Meisheng Zhou

发明人： Fumitake Mieno ,  Meisheng Zhou

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/78 ,  H01L29/1083 ,  H01L29/66636

摘要： A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction.

摘要翻译： 半导体器件及其制造方法包括使用固相外延（SPE）工艺形成的源极/漏极区域，以提供部分隔离的源极/漏极晶体管。 源极/漏极区域的非晶半导体材料结晶，然后通过退火而收缩，以在沟道方向施加拉伸应力。

公开(公告)号：US08872243B2

公开(公告)日：2014-10-28

申请号：US13618004

申请日：2012-09-14

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L29/76 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/302

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A semiconductor device manufacturing method includes providing a mask on a semiconductor member. The method further includes providing a dummy element to cover a portion of the mask that overlaps a first portion of the semiconductor member and to cover a second portion of the semiconductor member. The method further includes removing a third portion of the semiconductor member, which has not been covered by the mask or the dummy element. The method further includes providing a silicon compound that contacts the first portion of the semiconductor member. The method further includes removing the dummy element to expose and to remove the second portion of the semiconductor member. The method further includes forming a gate structure that overlaps the first portion of the semiconductor member. The first portion of the semiconductor member is used as a channel region and is supported by the silicon compound.

摘要翻译： 半导体器件制造方法包括在半导体部件上设置掩模。 该方法还包括提供虚拟元件以覆盖与半导体部件的第一部分重叠并覆盖半导体部件的第二部分的掩模的一部分。 该方法还包括去除未被掩模或虚拟元件覆盖的半导体部件的第三部分。 该方法还包括提供接触半导体部件的第一部分的硅化合物。 该方法还包括去除虚设元件以暴露并移除半导体部件的第二部分。 该方法还包括形成与半导体部件的第一部分重叠的栅极结构。 半导体部件的第一部分用作沟道区域并由硅化合物支撑。

公开(公告)号：US08420466B2

公开(公告)日：2013-04-16

申请号：US12259165

申请日：2008-10-27

申请人： Fumitake Mieno

发明人： Fumitake Mieno

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/44 ,  H01L29/76 ,  H01L29/788

CPC分类号： H01L29/788 ,  H01L29/66757 ,  H01L29/66825 ,  H01L29/7881

摘要： A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P− polysilicon layer overlying the co-planar surface and a floating gate on the P− polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P+ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

摘要翻译： 提供一种具有薄膜晶体管（TFT）浮动栅极存储单元结构的器件。 该器件包括衬底，衬底上的电介质层，以及嵌入电介质层中的一个或多个源极或漏极区域。 介电层与第一表面相关联。 所述一个或多个源区或漏区中的每一个包括在第一导电层上的扩散阻挡层上的N +多晶硅层。 N +多晶硅层具有与第一表面基本共面的第二表面。 另外，该器件包括覆盖共面表面的P-多晶硅层和P-多晶硅层上的浮置栅极。 浮栅是由底部氧化物隧道层和上部氧化物阻挡层夹在中间的低压CVD沉积硅层。 此外，该器件包括至少一个由覆盖在上氧化物块层上的P +多晶硅层制成的控制栅极。 提供了制造相同存储单元结构的方法，并且可以重复三维地集成结构。