公开(公告)号：US20120267708A1

公开(公告)日：2012-10-25

申请号：US13234150

申请日：2011-09-16

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Jing-Qing Chan ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Jing-Qing Chan ,  Yi-Chun Shih

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L21/2256 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/66727

摘要： A termination structure for a power MOSFET device includes a substrate, an epitaxial layer on the substrate, a trench in the epitaxial layer, a first insulating layer within the trench, a first conductive layer atop the first insulating layer, and a column doping region in the epitaxial layer and in direct contact with the first conductive layer. The first conductive layer is in direct contact with the first insulating layer and is substantially level with a top surface of the epitaxial layer. The first conductive layer comprises polysilicon, titanium, titanium nitride or aluminum.

摘要翻译： 功率MOSFET器件的端接结构包括衬底，衬底上的外延层，外延层中的沟槽，沟槽内的第一绝缘层，第一绝缘层顶部的第一导电层和第一绝缘层中的列掺杂区 外延层并与第一导电层直接接触。 第一导电层与第一绝缘层直接接触并且基本上与外延层的顶表面平齐。 第一导电层包括多晶硅，钛，氮化钛或铝。

公开(公告)号：US08541278B2

公开(公告)日：2013-09-24

申请号：US13234132

申请日：2011-09-15

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7811 ,  H01L29/7813

摘要： A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

公开(公告)号：US08357972B2

公开(公告)日：2013-01-22

申请号：US13227472

申请日：2011-09-07

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7803 ,  H01L29/7809

摘要： A semiconductor power device includes a substrate, a first semiconductor layer on the substrate, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer. At least a recessed epitaxial structure is disposed within a cell region and the recessed epitaxial structure may be formed in a pillar or stripe shape. A first vertical diffusion region is disposed in the third semiconductor layer and the recessed epitaxial structure is surrounded by the first vertical diffusion region. A source conductor is disposed on the recessed epitaxial structure and a trench isolation is disposed within a junction termination region surrounding the cell region. In addition, the trench isolation includes a trench, a first insulating layer on an interior surface of the trench, and a conductive layer filled into the trench, wherein the source conductor connects electrically with the conductive layer.

摘要翻译： 半导体功率器件包括衬底，衬底上的第一半导体层，第一半导体层上的第二半导体层以及第二半导体层上的第三半导体层。 至少凹入的外延结构设置在单元区域内，并且凹入的外延结构可以形成为柱状或条形。 第一垂直扩散区域设置在第三半导体层中，并且凹入的外延结构被第一垂直扩散区域包围。 源极导体设置在凹陷的外延结构上，并且沟槽隔离设置在围绕电池区的连接终端区域内。 此外，沟槽隔离包括沟槽，在沟槽的内表面上的第一绝缘层和填充到沟槽中的导电层，其中源极导体与导电层电连接。

公开(公告)号：US20120252176A1

公开(公告)日：2012-10-04

申请号：US13349038

申请日：2012-01-12

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC分类号： H01L21/336

CPC分类号： H01L29/7802 ,  H01L21/2253 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/1095

摘要： A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.

摘要翻译： 一种制造功率晶体管的方法包括：（a）在第一电气类型的衬底中形成沟槽; （b）从沟槽将第二电气载体扩散到衬底中，使得衬底形成为第一部分，第二部分与第二电气型载流子扩散并邻接沟槽，第一和第二部分是晶体 格子相互连续; （c）在所述沟槽中形成填充部分，所述填充部分邻接所述第二部分; （d）在第二部分和填充部分中执行载体植入过程; 和（e）在衬底上形成具有电介质层和导电层的栅极结构。

公开(公告)号：US08178410B1

公开(公告)日：2012-05-15

申请号：US13171368

申请日：2011-06-28

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Jing-Qing Chan ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Jing-Qing Chan ,  Yi-Chun Shih

IPC分类号： H01L21/8236

CPC分类号： H01L27/088 ,  H01L21/2255 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7811

摘要： A method for forming a power device includes the following steps. An epitaxial layer is formed on a substrate. A pad layer and hard mask are formed on the epitaxial layer. A trench is etched into the hard mask, the pad layer, and the epitaxial layer. The hard mask is removed. A buffer layer is formed on the sidewall of the trench. The trench is then filled with a dopant source layer comprising plural dopants. A drive-in process is performed to diffuse the dopants into the epitaxial layer through the buffer layer, thereby forming a diffusion region around the trench.

摘要翻译： 一种形成功率器件的方法包括以下步骤。 在衬底上形成外延层。 在外延层上形成焊盘层和硬掩模。 将沟槽蚀刻到硬掩模，焊盘层和外延层中。 硬面膜被去除。 缓冲层形成在沟槽的侧壁上。 然后用包括多个掺杂剂的掺杂剂源层填充沟槽。 执行驱入过程以通过缓冲层将掺杂剂扩散到外延层中，从而在沟槽周围形成扩散区域。

公开(公告)号：US08890253B2

公开(公告)日：2014-11-18

申请号：US13348961

申请日：2012-01-12

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7808

摘要： A semiconductor device includes: a substrate including a first epitaxial layer that has a first electrical type, and a second epitaxial layer; a transistor that includes a source region and an insulating spacer; an inner surrounding structure including an annular trench and an insulating spacer; an outer surrounding structure that has a second electrical type opposite to the first electrical type, and that is disposed adjacent to an upper surface of the second epitaxial layer to surround and contact the inner surrounding structure; and a conductive structure connecting to the source region, and the inner and outer surrounding structures.

摘要翻译： 半导体器件包括：包括具有第一电型的第一外延层和第二外延层的衬底; 晶体管，其包括源极区域和绝缘间隔物; 包括环形沟槽和绝缘垫片的内部周围结构; 外周围结构具有与第一电气类型相反的第二电气类型，并且邻近第二外延层的上表面设置以围绕和接触内周围结构; 以及连接到源极区域的导电结构以及内部和外部周围结构。

公开(公告)号：US08404531B2

公开(公告)日：2013-03-26

申请号：US13349038

申请日：2012-01-12

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

IPC分类号： H01L21/337

CPC分类号： H01L29/7802 ,  H01L21/2253 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/1095

摘要： A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.

摘要翻译： 一种制造功率晶体管的方法包括：（a）在第一电气类型的衬底中形成沟槽; （b）从沟槽将第二电型载体扩散到衬底中，使得衬底形成为第一部分，第二部分与第二电气型载流子扩散并邻接沟槽，第一和第二部分是晶体 格子相互连续; （c）在所述沟槽中形成填充部分，所述填充部分邻接所述第二部分; （d）在第二部分和填充部分中执行载体植入过程; 和（e）在衬底上形成具有电介质层和导电层的栅极结构。

公开(公告)号：US20120295410A1

公开(公告)日：2012-11-22

申请号：US13234132

申请日：2011-09-15

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7811 ,  H01L29/7813

摘要： A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

摘要翻译： 用于制造具有减小的米勒电容的超结半导体功率器件的方法包括以下步骤。 提供了N型衬底，并且在N型衬底上形成P型外延层。 至少在P型外延层中形成沟槽，随后在沟槽的内表面上形成缓冲层。 将N型掺杂剂层填充到沟槽中，然后蚀刻N型掺杂剂层以在沟槽的上部形成凹陷结构。 形成栅极氧化层，同时，N型掺杂剂层中的掺杂剂扩散到P型外延层中，形成N型扩散层。 最后，将栅极导体填充到凹陷结构中，并且在P型外延层中的栅极导体周围形成N型源极掺杂区。

公开(公告)号：US20130203229A1

公开(公告)日：2013-08-08

申请号：US13537080

申请日：2012-06-29

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

IPC分类号： H01L21/336 ,  H01L21/322

CPC分类号： H01L29/7802 ,  H01L21/02238 ,  H01L21/2255 ,  H01L21/30604 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66727

摘要： The present invention provides a method of reducing a surface doping concentration of a doped diffusion region. First, a semiconductor substrate is provided. The semiconductor substrate has the doped diffusion region disposed therein, and the doped diffusion region is in contact with a surface of the semiconductor substrate. A doping concentration of the doped diffusion region close to the surface is larger than a doping concentration of the doped diffusion region away from the surface. Then, a thermal oxidation process is performed to form an oxide layer on the surface of the semiconductor substrate. A part of the doped diffusion region in contact with the surface reacts with oxygen to form a part of the oxide layer. Then, the oxide layer is removed.

摘要翻译： 本发明提供了降低掺杂扩散区域的表面掺杂浓度的方法。 首先，提供半导体基板。 半导体衬底具有设置在其中的掺杂扩散区，并且掺杂扩散区与半导体衬底的表面接触。 接近表面的掺杂扩散区域的掺杂浓度大于掺杂扩散区域远离表面的掺杂浓度。 然后，进行热氧化处理，以在半导体衬底的表面上形成氧化物层。 与表面接触的掺杂扩散区的一部分与氧反应形成氧化物层的一部分。 然后，除去氧化物层。

公开(公告)号：US20130153994A1

公开(公告)日：2013-06-20

申请号：US13556166

申请日：2012-07-23

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Chia-Hao Chang

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66734 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/6653 ,  H01L29/7813

摘要： The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate.

摘要翻译： 本发明提供一种具有超结的沟槽型功率晶体管器件的制造方法。 首先，提供第一导电类型的衬底，然后在衬底上形成第二导电类型的外延层。 接下来，在外延层中形成通孔，并且通孔穿过外延层。 然后分别在通孔的两侧在外延层中形成第一导电类型的两个掺杂漏极区，并且掺杂漏极区从外延层的顶表面延伸以与衬底接触。