公开(公告)号：US07388405B2

公开(公告)日：2008-06-17

申请号：US11513239

申请日：2006-08-31

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03B1/00

CPC分类号： H03K19/018571 ,  H03F1/0261 ,  H03F3/505 ,  H03F2200/18 ,  H04L25/028

摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

摘要翻译： 源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。 因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。 因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器 使用输入数据信号从低电平变为高电平时的一个时钟周期。 两个来源追随者在适当的时机运行。

公开(公告)号：US20060176091A1

公开(公告)日：2006-08-10

申请号：US11289753

申请日：2005-11-30

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

公开(公告)号：US20100225518A1

公开(公告)日：2010-09-09

申请号：US12376400

申请日：2007-06-19

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Kurumi Nakayama

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Kurumi Nakayama

IPC分类号： H03M1/66

CPC分类号： G09G3/3685 ,  G09G3/3696 ,  G09G2310/027 ,  H03M1/76

摘要： A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

摘要翻译： 选择部（105）选择与数字数据（D-DATA）的数字值对应的，具有逐步变化的电压值的多个阶梯电压（SV1，SV2，SV3 ......等）中的阶梯电压。 对于多个步进电压（SV1，SV2，SV3 ...）中的每一个，将不同的数字值分配给步进电压的不同步骤。 放大器部分（106）放大由选择部分（105）选择的步进电压。 输出部分（107）输出由放大器部分（106）放大的阶跃电压作为对应于数字数据（D-DATA）的数字值的时间周期的输出电压（Vout）。

公开(公告)号：US07705645B2

公开(公告)日：2010-04-27

申请号：US12033707

申请日：2008-02-19

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延迟到参考时钟信号的下降（或上升）的间隔期间。

公开(公告)号：US20070121761A1

公开(公告)日：2007-05-31

申请号：US11514151

申请日：2006-09-01

申请人： Shiro Dosho ,  Shiro Sakiyama ,  Yusuke Tokunaga ,  Seiji Watanabe ,  Hiroshi Koshida

发明人： Shiro Dosho ,  Shiro Sakiyama ,  Yusuke Tokunaga ,  Seiji Watanabe ,  Hiroshi Koshida

IPC分类号： H04L27/22

CPC分类号： H03K5/13 ,  H03K5/15013 ,  H03K2005/00052 ,  H03K2005/00273

摘要： A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.

摘要翻译： 相位调整电路包括第一至第二相位调整电路。 每个两相调节电路包括用于执行两个输入信号的逻辑和的第一逻辑电路，用于执行两个输入信号的逻辑积的第二逻辑电路，具有等于第二逻辑电路的信号延迟的信号延迟的第一延迟电路 并且被配置为延迟从第一逻辑电路输出的信号;以及第二延迟电路，其具有等于第一逻辑电路的信号延迟的信号延迟，并且被配置为延迟从第二逻辑电路输出的信号。 在一定阶段从两相调节电路中输出的两个信号在下一级输入到两相调节电路之一。

公开(公告)号：US07936295B2

公开(公告)日：2011-05-03

申请号：US12376400

申请日：2007-06-19

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Kurumi Nakayama

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Kurumi Nakayama

IPC分类号： H03M1/78

CPC分类号： G09G3/3685 ,  G09G3/3696 ,  G09G2310/027 ,  H03M1/76

摘要： A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

摘要翻译： 选择部（105）选择与数字数据（D-DATA）的数字值对应的，具有逐步变化的电压值的多个阶梯电压（SV1，SV2，SV3 ......等）中的阶梯电压。 对于多个步进电压（SV1，SV2，SV3 ...）中的每一个，将不同的数字值分配给步进电压的不同步骤。 放大器部分（106）放大由选择部分（105）选择的步进电压。 输出部分（107）输出由放大器部分（106）放大的阶跃电压作为对应于数字数据（D-DATA）的数字值的时间周期的输出电压（Vout）。

公开(公告)号：US07911369B2

公开(公告)日：2011-03-22

申请号：US12600784

申请日：2008-08-21

申请人： Takashi Morie ,  Kazuo Matsukawa ,  Shiro Sakiyama ,  Shiro Dosho ,  Yusuke Tokunaga

发明人： Takashi Morie ,  Kazuo Matsukawa ,  Shiro Sakiyama ,  Shiro Dosho ,  Yusuke Tokunaga

IPC分类号： H03M1/38

CPC分类号： H03M1/0678 ,  H03M1/0695 ,  H03M1/44

摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.

摘要翻译： 流水线式AD转换器（1）包括多个转换级（11,11 ...）。 在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。 数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。 充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2） 以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。 放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

公开(公告)号：US20100149010A1

公开(公告)日：2010-06-17

申请号：US12600784

申请日：2008-08-21

申请人： Takashi Morie ,  Kazuo Matsukawa ,  Shiro Sakiyama ,  Shiro Dosho ,  Yusuke Tokunaga

发明人： Takashi Morie ,  Kazuo Matsukawa ,  Shiro Sakiyama ,  Shiro Dosho ,  Yusuke Tokunaga

IPC分类号： H03M1/38 ,  H03M1/00

CPC分类号： H03M1/0678 ,  H03M1/0695 ,  H03M1/44

摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.

摘要翻译： 流水线式AD转换器（1）包括多个转换级（11,11 ...）。 在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。 数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。 充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2） 以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。 放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

公开(公告)号：US20070183175A1

公开(公告)日：2007-08-09

申请号：US11637687

申请日：2006-12-13

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

IPC分类号： H02M7/00

CPC分类号： H02M3/07 ,  H03L7/0895 ,  H03L7/0896

摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.

摘要翻译： 电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。 推挽操作中的另一个用电流镜电路的输出电流进行。

公开(公告)号：US08040168B2

公开(公告)日：2011-10-18

申请号：US11188855

申请日：2005-07-26

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

IPC分类号： H03L7/06 ,  G05F3/02

CPC分类号： H02M3/07

摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

摘要翻译： 电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。 另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。