公开(公告)号：USRE39120E1

公开(公告)日：2006-06-06

申请号：US10124067

申请日：2002-04-16

申请人： Yoshihisa Sechi ,  Masahiro Sato ,  Hiroshi Aida ,  Shoji Kohsaka ,  Yutaka Hayashi

发明人： Yoshihisa Sechi ,  Masahiro Sato ,  Hiroshi Aida ,  Shoji Kohsaka ,  Yutaka Hayashi

IPC分类号： C04B35/195

CPC分类号： H01L23/15 ,  C04B35/195 ,  H01L2924/0002 ,  H01L2924/00

摘要： Low thermal expansion ceramics contains a cordierite crystal phase, wherein a phase of a crystalline compound containing at least one element selected from the group consisting of an alkaline earth element other than Mg, a rare earth element, Ga and In, is precipitated in the grain boundaries of said crystal phase, said ceramics has a relative density of not smaller than 95%, a coefficient of thermal expansion of not larger than 1×10−6/° C. at 10 to 40° C., and a Young's modulus of not smaller than 130 GPa. That is, the ceramics has a small coefficient of thermal expansion, is deformed very little depending upon a change in the temperature, has a very high Young's modulus and is highly rigid and is resistance against external force such as vibration. Accordingly, the ceramics is very useful as a member for supporting a wafer or an optical system is a lithography apparatus that forms high resolution circuit patterns on a silicon wafer.

摘要翻译： 低热膨胀陶瓷含有堇青石结晶相，其中含有选自Mg以外的碱土金属元素，稀土元素，Ga和In中的至少一种元素的结晶化合物的相析出在晶粒中 所述晶相的边界，所述陶瓷的相对密度不低于95％，热膨胀系数在10-40℃下不大于1×10 -6 /℃， 杨氏模量不小于130GPa。 也就是说，陶瓷具有小的热膨胀系数，根据温度的变化而变形很小，具有非常高的杨氏模量，并且是高度刚性的并且是抗外力如振动的抵抗力。 因此，陶瓷作为用于支撑晶片的部件是非常有用的，或者光学系统是在硅晶片上形成高分辨率电路图案的光刻设备。

公开(公告)号：US20050221553A1

公开(公告)日：2005-10-06

申请号：US11092794

申请日：2005-03-29

申请人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

发明人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885 ,  H01L29/7883

摘要： In a non-volatile memory in which a floating gate is provided above a single crystal control region, a potential of wiring, which is arranged above the floating gate, has a capacitive coupling with respect to the floating gate, or even one part in and on an insulating film on the floating gate is included or attached with electric charge, thereby varying the gate threshold voltage of the floating gate non-volatile memory measured from the single crystal control region. In order to solve the above-described problems, the present invention provides following methods. A shield conductive film is provided above a floating gate through a shield insulating film. For the shield insulating film, there is used an insulating film formed by not a deposition method in which a gas atmosphere containing un-balanced charge particles such as excess electrons or excess ions contacts with a wafer surface, such as plasma CVD but a deposition method in which neutral molecules/atoms come flying immediately above the wafer, for example, thermal CVD, radical CVD, photo-assisted CVD, or thermal oxidization.

摘要翻译： 在浮动栅极设置在单晶体控制区域之上的非易失性存储器中，布置在浮置栅极上方的布线电位具有相对于浮动栅极的电容耦合，或甚至一个部分 在浮栅上的绝缘膜上包含或附加电荷，从而改变从单晶控制区测量的浮栅非易失性存储器的栅极阈值电压。 为了解决上述问题，本发明提供以下方法。 屏蔽导电膜通过屏蔽绝缘膜设置在浮栅上。 对于屏蔽绝缘膜，使用通过不是沉积方法形成的绝缘膜，其中包含诸如过电子或过量离子的非平衡电荷颗粒的气体气氛与晶片表面接触，诸如等离子体CVD，但是沉积方法 其中中性分子/原子直接在晶片上方飞行，例如热CVD，自由基CVD，光辅助CVD或热氧化。

公开(公告)号：US20050111279A1

公开(公告)日：2005-05-26

申请号：US10756568

申请日：2004-01-13

申请人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

发明人： Seiki Ogura ,  Yutaka Hayashi ,  Tomoko Ogura

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115

摘要： A fast low voltage ballistic program, ultra-short channel, ultra-high density, dual-bit multi-level flash memory is described with a two or three polysilicon split gate side wall process. The structure and operation of this invention is enabled by a twin MONOS cell structure having an ultra-short control gate channel of less than 40 nm, with ballistic injection which provides high electron injection efficiency and very fast program at low program voltages of 3˜5V. The cell structure is realized by (i) placing side wall control gates over a composite of Oxide-Nitride-Oxide (ONO) on both sides of the word gate, and (ii) forming the control gates and bit diffusion by self-alignment and sharing the control gates and bit diffusions between memory cells for high density. Key elements used in this process are: 1) Disposable side wall process to fabricate the ultra short channel and the side wall control gate with or without a step structure, and 2) Self-aligned definition of the control gate over the storage nitride and the bit line diffusion, which also runs in the same direction as the control gate. The features of fast program, low voltage, ultra-high density, dual-bit, multi-level MONOS NVRAM of the present invention include: 1) Electron memory storage in nitride regions within an ONO layer underlying the control gates, 2) high density dual-bit cell in which there are two nitride memory storage elements per cell, 3) high density dual-bit cell can store multi-levels in each of the nitride regions, 4) low current program controlled by the word gate and control gate, 5) fast, low voltage program by ballistic injection utilizing the controllable ultra-short channel MONOS, and 6) side wall control poly gates to program and read multi-levels while masking out memory storage state effects of the unselected adjacent nitride regions and memory cells. The ballistic MONOS memory cell is arranged in the following array: each memory cell contains two nitride regions for one word gate, and ½ a source diffusion and ½ a bit diffusion. Control gates can be defined separately or shared together over the same diffusion. Diffusions are shared between cells and run in parallel to the side wall control gates, and perpendicular to the word line.

公开(公告)号：US06804149B2

公开(公告)日：2004-10-12

申请号：US10101659

申请日：2002-03-20

申请人： Seiki O. Ogura ,  Yutaka Hayashi

发明人： Seiki O. Ogura ,  Yutaka Hayashi

IPC分类号： G11C1604

CPC分类号： H01L21/28202 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/12 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7923

摘要： The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.

摘要翻译： 非易失性存储器单元和/或阵列技术领域本发明涉及一种非易失性存储单元和/或阵列，以及一种操作能够实现高集成密度，低电压编程和/或高速编程的高集成度非易失性存储器单元的方法， 在衬底10的表面中形成p阱101，并且沟道形成半导体区域110被限定在p阱101的表面中并被第一n +区121和第二n + +区域122.形成与第一n +区121接触的载体供给部（CS：载体供给）111，并且载体加速注入部112（AI：加速注入）接触 在沟道形成半导体区域110中的第二n +区域122，其中载体供给部分111和载流子加速注入部分112彼此接触。

公开(公告)号：US06534812B1

公开(公告)日：2003-03-18

申请号：US09487919

申请日：2000-01-19

申请人： Mikio Mukai ,  Yutaka Hayashi

发明人： Mikio Mukai ,  Yutaka Hayashi

IPC分类号： H01L27108

CPC分类号： H01L27/1203 ,  H01L27/108

摘要： A memory cell with a stored charge on its gate comprising; (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, (E) a first non-linear resistance element having two ends, one end being connected to the first gate, and (F) a second non-linear resistance element composed of the first gate, the insulation layer and either the channel-forming region and at least one of the source/drain regions.

摘要翻译： 在其门上具有存储电荷的存储单元包括： （A）沟道形成区域，（B）形成在形成在沟道形成区域的表面上的绝缘层上的第一栅极，第一栅极和沟道形成区域通过绝缘层彼此面对，（C）第二栅极 与第一栅极电容耦合的栅极，（D）与沟道形成区域接触形成的源极/漏极区域，一个源极/漏极区域彼此间隔开，（E）具有两个端部的第一非线性电阻元件，一个 和（F）由第一栅极，绝缘层和沟道形成区域以及源极/漏极区域中的至少一个组成的第二非线性电阻元件。

公开(公告)号：US06501110B1

公开(公告)日：2002-12-31

申请号：US09552617

申请日：2000-04-19

申请人： Mikio Mukai ,  Toshio Kobayashi ,  Yutaka Hayashi

发明人： Mikio Mukai ,  Toshio Kobayashi ,  Yutaka Hayashi

IPC分类号： H01L2976

CPC分类号： G11C11/405

摘要： A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

摘要翻译： 一种半导体存储单元，包括用于读出的第一晶体管，用于切换的第二晶体管，并且具有第一区域，形成在所述第一区域的表面区域中的第二区域，形成在所述第二区域的表面区域中的第三区域， 第四区域形成在第一区域的表面区域中并且与第二区域隔开，形成在第四区域的表面区域中的第五区域和栅极区域，其中当半导体存储单元被切割成第一虚拟垂直平面 其垂直于栅极区域的延伸方向并且通过栅极区域的中心，栅极区域附近的第二区域和第四区域相对于并联的第二假想垂直平面几乎对称 与栅极区域的延伸方向并通过栅极区域的中心。

公开(公告)号：US06426790B1

公开(公告)日：2002-07-30

申请号：US09514584

申请日：2000-02-28

申请人： Yutaka Hayashi

发明人： Yutaka Hayashi

IPC分类号： G03B2758

CPC分类号： G03F7/7095 ,  G03F7/70358 ,  G03F7/70725 ,  G03F7/70775 ,  G03F7/70833

摘要： A stage apparatus of the invention comprises: a holder for holding a substrate, and a position detection device for detecting a position of the substrate, based on reflected light from a mobile mirror provided at a predetermined positional relationship with the holder. The holder and a base material of the mobile mirror consist of ceramics having a coefficient of thermal expansion of 1×10−6/° C. or less. With such an apparatus, costs related to temperature control can be reduced.

摘要翻译： 本发明的舞台装置包括：基于用于保持衬底的保持器和用于基于与保持器以预定位置关系设置的来自移动镜的反射光来检测衬底的位置的位置检测装置。 移动镜的支架和基材由具有1×10-6 /℃或更低的热膨胀系数的陶瓷组成。 利用这样的装置，可以降低与温度控制有关的成本。

公开(公告)号：US06285546B1

公开(公告)日：2001-09-04

申请号：US09450380

申请日：1999-11-29

申请人： Michihito Watarai ,  Yutaka Hayashi ,  Mitsuo Miyamoto ,  Kazuhiro Matsuo ,  Eiji Kadomoto ,  Koji Nakayama ,  Akihiro Sakurai ,  Shigeyasu Tsubaki

发明人： Michihito Watarai ,  Yutaka Hayashi ,  Mitsuo Miyamoto ,  Kazuhiro Matsuo ,  Eiji Kadomoto ,  Koji Nakayama ,  Akihiro Sakurai ,  Shigeyasu Tsubaki

IPC分类号： H05K720

CPC分类号： H05K7/20736

摘要： An electronic device has a frame and a back board having plural logical units and power supply units mounted thereon. The logical units and the power supply units are alternately located on both sides of the back board in the center of the frame so that the power supply units mounted on one side of the back board may feed a power to the closest logical units mounted on the other side. Further, the air flow paths to be circulated through the logical units and the power supply units are formed so that each unit may be efficiently cooled by the air fed by an air fan unit. As a result, the feeding voltage becomes uniform and the cooling efficiency is improved.

摘要翻译： 电子设备具有框架和背板，其具有多个逻辑单元和安装在其上的电源单元。 逻辑单元和电源单元交替地位于框架中心的背板的两侧，使得安装在背板的一侧上的电源单元可以将电力馈送到安装在背板上的最接近的逻辑单元 另一边。 此外，通过逻辑单元和电源单元循环的空气流动路径被形成为使得每个单元可以被由空气风扇单元供给的空气有效地冷却。 结果，供电电压变得均匀，并且提高了冷却效率。

公开(公告)号：US06255166B1

公开(公告)日：2001-07-03

申请号：US09473031

申请日：1999-12-28

申请人： Seiki Ogura ,  Yutaka Hayashi

发明人： Seiki Ogura ,  Yutaka Hayashi

IPC分类号： H01L21336

CPC分类号： H01L21/28202 ,  G11C16/0466 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/12 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： Provided in the present invention are a high speed and low program voltage nonvolatile memory cell, a programming method for same and a nonvolatile memory array. A nonvolatile memory cell comprises a first gate insulator formed on a surface of a first channel forming semiconductor region adjacent to a source region; a second gate insulator formed on a surface of a second channel forming semiconductor region adjacent to a drain region; a first gate electrode formed on said first gate insulator; and a second gate electrode formed on said second gate insulator wherein the second gate insulator includes a first layer forming a potential barrier at the interface with the second channel forming region; a third layer forming a potential barrier at the interface with the second gate electrode and the second layer between the first and third layers forming a carrier trapping level.

摘要翻译： 在本发明中提供了一种高速和低编程电压的非易失性存储单元，一种用于其的编程方法和一种非易失性存储器阵列。 非易失性存储单元包括形成在与源极区域相邻的形成半导体区域的第一沟道的表面上的第一栅极绝缘体; 形成在与漏极区相邻的形成半导体区域的第二沟道的表面上的第二栅极绝缘体; 形成在所述第一栅极绝缘体上的第一栅电极; 以及形成在所述第二栅极绝缘体上的第二栅电极，其中所述第二栅绝缘体包括在与所述第二沟道形成区的界面处形成势垒的第一层; 在与第二栅电极的界面处形成势垒的第三层和形成载流子俘获电平的第一和第三层之间的第二层。

公开(公告)号：US5825064A

公开(公告)日：1998-10-20

申请号：US25822

申请日：1993-03-03

申请人： Yutaka Hayashi ,  Yoshikazu Kojima ,  Ryoji Takada ,  Masaaki Kamiya

发明人： Yutaka Hayashi ,  Yoshikazu Kojima ,  Ryoji Takada ,  Masaaki Kamiya

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C14/00 ,  G11C16/04 ,  G11C27/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： G11C27/005 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C14/00

摘要： The semiconductor nonvolatile memory has integrated memory cells, each being operative to carry out writing and reading of information in random-access basis and having an electric charge storage structure effective to memorize the information in nonvolatile state. The information is temporarily written into each memory cell in volatile state, and thereafter the temporarily written information is written at one into the respective electric charge storage structure of each memory cell, thereby effecting quick writing of nonvolatile information into the respective memory cells of multi-bits.

摘要翻译： 半导体非易失性存储器具有集成存储单元，每个存储单元可操作以在随机存取的基础上进行信息的写入和读取，并且具有有效地将信息存储在非易失性状态的电荷存储结构。 该信息以易失性状态临时写入每个存储单元，之后将临时写入的信息一个写入每个存储单元的各个电荷存储结构中，从而将非易失性信息快速写入到多个存储单元的各个存储单元中， 位。