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公开(公告)号：US12218637B2
公开(公告)日：2025-02-04
申请号：US18534153
申请日：2023-12-08
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号：US11848648B2
公开(公告)日：2023-12-19
申请号：US17573375
申请日：2022-01-11
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
CPC classification number: H03F1/223 , H03F1/26 , H03F3/193 , H03F3/68 , H04L27/2647 , H03F1/0277 , H03F2200/294 , H03F2200/489
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号：US20220209719A1
公开(公告)日：2022-06-30
申请号：US17573375
申请日：2022-01-11
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号：US11025207B2
公开(公告)日：2021-06-01
申请号：US16563481
申请日：2019-09-06
Applicant: pSemi Corporation
Inventor： Kashish Pal , John Birkbeck
Abstract: Various methods and circuital arrangements for biasing gates of stacked transistors of a cascode amplifier are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback voltage that is based on a sensed voltage at one or more nodes of a replica circuit of the stacked transistors, the amplifier and the replica circuit biased with same gate voltages. According to one aspect, one gate voltage is adjusted based on a comparison of the feedback voltage with a reference voltage, and other gate voltages are derived by offsetting of the one gate voltage with voltages generated by a current flow through a resistive ladder network.
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15.发明申请公开(公告)号：US20190372528A1
公开(公告)日：2019-12-05
申请号：US15991980
申请日：2018-05-29
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20190296718A1
公开(公告)日：2019-09-26
申请号：US16372194
申请日：2019-04-01
Applicant: pSemi Corporation
Inventor： John Birkbeck , Vikas Sharma , Kashish Pal , Mark James O'Leary
Abstract: A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.
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公开(公告)号：US20190158029A1
公开(公告)日：2019-05-23
申请号：US16240601
申请日：2019-01-04
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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公开(公告)号：US10027283B2
公开(公告)日：2018-07-17
申请号：US15258806
申请日：2016-09-07
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal , Arun Srikanth Peri
Abstract: Various methods and circuital arrangements for controlling an RF amplifier while reducing size, cost and power consumption are presented. Included is an amplifier controller unit that provides different current amplification stages that can be used for calibrating an output power of the RF amplifier based on a reference current. Order of the current amplification stages starting from the reference current allow reduction in size, cost and power consumption.
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19.发明公开公开(公告)号：US20240186958A1
公开(公告)日：2024-06-06
申请号：US18534153
申请日：2023-12-08
Applicant: pSemi Corporation
Inventor： Kashish Pal , Emre Ayranci , Miles Sanner
CPC classification number: H03F1/223 , H03F1/26 , H03F3/193 , H03F3/68 , H04L27/2647 , H03F1/0277 , H03F2200/294 , H03F2200/489
Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.
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公开(公告)号：US11984852B2
公开(公告)日：2024-05-14
申请号：US18328987
申请日：2023-06-05
Applicant: pSemi Corporation
Inventor： Poojan Wagh , Kashish Pal
CPC classification number: H03F1/0227 , H03F1/223 , H03F1/301 , H03F1/56 , H03F3/189 , H03F3/193 , H03F2200/18 , H03F2200/249 , H03F2200/453
Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.
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