Calibration apparatus and method for sampler with adjustable high frequency gain

    公开(公告)号:US10679716B2

    公开(公告)日:2020-06-09

    申请号:US16363785

    申请日:2019-03-25

    申请人: Kandou Labs, S.A.

    摘要: Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

    High performance phase locked loop
    12.
    发明授权

    公开(公告)号:US10587394B2

    公开(公告)日:2020-03-10

    申请号:US16533594

    申请日:2019-08-06

    申请人: Kandou Labs, S.A.

    发明人: Armin Tajalli

    摘要: Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

    Low power chip-to-chip bidirectional communications

    公开(公告)号:US10581644B2

    公开(公告)日:2020-03-03

    申请号:US16174147

    申请日:2018-10-29

    申请人: Kandou Labs, S.A.

    发明人: Ali Hormati

    摘要: Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

    Circuits for efficient detection of vector signaling codes for chip-to-chip communication

    公开(公告)号:US10560293B2

    公开(公告)日:2020-02-11

    申请号:US16225206

    申请日:2018-12-19

    申请人: Kandou Labs, S.A.

    摘要: In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

    Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation

    公开(公告)号:US10554380B2

    公开(公告)日:2020-02-04

    申请号:US15881509

    申请日:2018-01-26

    申请人: Kandou Labs, S.A.

    发明人: Armin Tajalli

    摘要: Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

    Method and apparatus for high speed chip-to-chip communications

    公开(公告)号:US10243765B2

    公开(公告)日:2019-03-26

    申请号:US15615262

    申请日:2017-06-06

    申请人: Kandou Labs, S.A.

    IPC分类号: H04L25/49 H04L25/02

    摘要: Described herein are systems and methods of receiving first and second input signals at a first two-input comparator, responsively generating a first subchannel output, receiving third and fourth input signals at a second two-input comparator, responsively generating a second subchannel output, receiving the first, second, third, and fourth input signals at a third multi-input comparator, responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals, configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to a legacy mode of operation and a P4 mode of operation.

    Method and system for calibrating multi-wire skew

    公开(公告)号:US10243614B1

    公开(公告)日:2019-03-26

    申请号:US15881512

    申请日:2018-01-26

    申请人: Kandou Labs, S.A.

    IPC分类号: H04B3/00 H04B3/462

    摘要: Methods and systems are described for receiving, over a plurality of consecutive signaling intervals, a plurality of codewords, each codeword received as a plurality of symbols via wires of a multi-wire bus, the plurality of symbols received at a plurality of multi-input comparators (MICs), wherein each symbol is received by at least two MICs, generating, for each codeword, a corresponding linear combination of the received symbols, generating a plurality of composite skew measurement signals over the plurality of consecutive signaling intervals, each composite skew measurement signal based on samples of one or more linear combinations, and updating wire-specific skew values of the wires of the multi-wire bus, wherein one or more wire-specific skew values are updated according to composite skew measurement signals associated with linear combinations formed by at least two different MICs.

    Clock data recovery with decision feedback equalization

    公开(公告)号:US10193716B2

    公开(公告)日:2019-01-29

    申请号:US15582545

    申请日:2017-04-28

    申请人: Kandou Labs, S.A.

    IPC分类号: H04L7/033 H04L25/03 H04L7/00

    摘要: Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error indication, the phase error indication selected in response to identification of a predetermined data decision pattern.