公开(公告)号：US4326095A

公开(公告)日：1982-04-20

申请号：US107714

申请日：1979-12-27

申请人： Teruo Yamaguchi

发明人： Teruo Yamaguchi

IPC分类号： H01L23/02 ,  H01L23/057 ,  H01L23/556 ,  H05K5/00 ,  H05K5/06

CPC分类号： H01L23/057 ,  H01L23/556 ,  H05K5/0095 ,  H01L2924/16152

摘要： A casing for a semiconductor memory chip comprises a barrier intercepting a limited space that envelopes lines of vision between an exposed surface of the chip and an inside end surface of a sealing layer for hermetically sealing a cap and a base member of the casing together and at least towards which alpha particles are emitted from the sealing layer inside surface. The barrier may be made integral with a base member peripheral region having a peripheral surface to be sealed to the cap member by the sealing layer, with that mounting surface of the base member on which the chip is attached, recessed relative to the peripheral surface. The peripheral surface may be either parallel to the mounting surface or canted so that the limited space may be directed inwardly away from the mounting surface. Alternatively, the barrier may comprise a pedestal member having a surface that is an outward extension of the mounting surface, with the mounting surface protruded relative to the peripheral surface. As a further alternative, the barrier may comprise a protrusion on at least one of the peripheral surface and a like surface of the cap member, with the protrusion or protrusions inwardly offset relative to the sealing layer inside surface.

摘要翻译： 一种用于半导体存储器芯片的壳体包括阻挡在芯片的暴露表面和密封层的内端表面之间包围视线的有限空间的屏障，用于将壳体和壳体的基底部件一起密封在一起并且在 最小的α粒子从密封层内表面发射出来。 阻挡层可以与具有通过密封层密封到盖构件的外周表面的基底构件周边区域一体地形成，其中附接有芯片的基底构件的安装表面相对于外围表面凹陷。 外周表面可以平行于安装表面或倾斜，使得有限的空间可以被引导向内远离安装表面。 或者，阻挡件可以包括具有作为安装表面的向外延伸的表面的基座构件，其中安装表面相对于外围表面突出。 作为另一替代方案，阻挡层可以包括在帽构件的外周表面和类似表面中的至少一个上的突起，其中突出部或突起相对于密封层内表面向内偏移。

公开(公告)号：US4323405A

公开(公告)日：1982-04-06

申请号：US105196

申请日：1979-12-19

申请人： Koichi Uno ,  Shinichi Murakami

发明人： Koichi Uno ,  Shinichi Murakami

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L23/02 ,  H01L23/057 ,  H01L23/556 ,  H01L27/06 ,  H01L23/06

CPC分类号： H01L23/057 ,  H01L23/556 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/1617 ,  Y10S438/953

摘要： A hermetic cap member of a casing for a semiconductor memory element is provided with a protection layer on a recessed surface facing the memory element. The protection layer is of at least one material which does not emit alpha particles and has a thickness sufficient to prevent alpha particles from being emitted from the cap member onto the memory element. Specifically, the protection layer may be a plate of a pertinent one of the following silicon of high purity, 42 alloy, or Kovar and is attached to the cap member by the use of an adhesive of glass frit. Alternatively, the protection layer may be made from a metallic paste of silver, silver-palladium, or gold-palladium by firing the same onto the cap member. The protection layer may also be magnesium oxide formed by the use of a plasma spray process. As a further alternative, the protection layer may consist of a plurality of materials.

摘要翻译： 用于半导体存储元件的壳体的密封盖构件在面向存储元件的凹入表面上设置有保护层。 保护层是至少一种不发射α粒子并且具有足以防止α粒子从盖构件发射到存储元件上的厚度的材料。 具体地，保护层可以是以下相关的高纯度硅，42合金或科瓦尔之一的板，并且通过使用玻璃料的粘合剂附接到盖构件。 或者，保护层可以由银，银 - 钯或金 - 钯的金属膏制成，通过将其烧制到盖构件上。 保护层也可以是通过使用等离子体喷涂工艺形成的氧化镁。 作为另一替代方案，保护层可以由多种材料组成。

公开(公告)号：US4098939A

公开(公告)日：1978-07-04

申请号：US688900

申请日：1976-05-21

申请人： Toshiro Kuroda ,  Susumu Kakami

发明人： Toshiro Kuroda ,  Susumu Kakami

IPC分类号： G09F9/33 ,  B32B3/00 ,  B32B7/14

CPC分类号： G09F9/33 ,  Y10S428/917 ,  Y10T428/24851 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/256 ,  Y10T428/265 ,  Y10T428/31678

摘要： A substrate assembly for a fluorescent or phosphorescent display panel comprises a layer of fired liquid gold, preferably three microns or less thick, for each of segmented display electrodes. The layer is in direct contact with an insulator substrate and with a mass of a luminescent material and may be an integral part of a lead for the electrode or electrodes. Alternatively, the layer may be formed on a resistive layer comprising powder of ruthenium (IV) oxide and formed, in turn, on the substrate with a conductive layer interposed for providing an electric connection to the lead.

公开(公告)号：US5209688A

公开(公告)日：1993-05-11

申请号：US672765

申请日：1991-03-20

申请人： Susumu Nishigaki ,  Syozo Ohtomo ,  Rikiya Kamimura ,  Kazunari Tanaka

发明人： Susumu Nishigaki ,  Syozo Ohtomo ,  Rikiya Kamimura ,  Kazunari Tanaka

IPC分类号： H01J17/49

CPC分类号： H01J17/492

摘要： A plasma display panel is disclosed, which comprises a pair of insulating substrates with a predetermined space therebetween; a group of anode electrodes and a group of cathode electrodes formed on the inner side of each of the insulating substrates in such a manner that the groups of the electrodes are normal to each other; and barriers formed on the insulating substrate having the anode electrodes thereon by photolithography. Since the barriers are formed by photolithography using an ultraviolet-curable resin or positive-type resist, high precison patterns having a line width of 100 .mu.m or less and a line spacing of 100 .mu.m or less can be easily obtained and, thereby, a high resolution plasma display having a decreased picture element area and a wider discharge space can be obtained. When photolithography is used in the formation of the cathode electrodes, further high precision fine patterns can be obtained and further finely detailed pitch of picture elements can be achieved.

摘要翻译： 公开了一种等离子体显示面板，其包括一对具有预定间隔的绝缘基板; 一组阳极电极和一组阴极电极，其形成在每个绝缘基板的内侧，使得电极组彼此正交; 以及通过光刻法在其上具有阳极电极的绝缘基板上形成的屏障。 由于通过使用紫外线固化型树脂或正型抗蚀剂的光刻法形成了阻挡层，所以容易得到线宽为100μm以下，线间隔为100μm以下的高精细图案， 可以获得具有减小的像素面积和更宽放电空间的高分辨率等离子体显示器。 当在形成阴极电极中使用光刻时，可以获得更高精度的精细图案，并且可以实现更精细的图像元素间距。

公开(公告)号：US4849384A

公开(公告)日：1989-07-18

申请号：US212168

申请日：1988-06-13

申请人： Kouichi Tatsuki ,  Kanji Murano ,  Susumu Nishigaki

发明人： Kouichi Tatsuki ,  Kanji Murano ,  Susumu Nishigaki

IPC分类号： C04B35/49 ,  C04B35/48 ,  H01B3/12 ,  H01P7/10

CPC分类号： H01P7/10

摘要： There is provided a dielectric porcelain used as dielectric resonator mainly in a microwave range. According to the present invention, 0.1 to 5.3 mol % of one or more of Tb.sub.4 O.sub.7, CeO.sub.2, TeO.sub.2, Gd.sub.2 O.sub.3 and Dy.sub.2 O.sub.3 as additive is admixed to a dielectric material Pb.sub.x Zr.sub.(1-x) O.sub.(2-x) wherein 0.42.ltoreq..ltoreq.0.69 to procure a dielectric constant while keeping the dielectric loss to a lower value and simultaneously controlling temperature characteristics of the dielectric constant, that is, temperature characteristics of the resonant frequency.

摘要翻译： 提供了一种主要用于微波范围的电介质陶瓷作为介质谐振器。 根据本发明，将0.1〜5.3mol％的Tb 4 O 7，CeO 2，TeO 2，Gd 2 O 3和Dy 2 O 3作为添加剂中的一种或多种掺入到介电材料PbxZr（1-x）O（2-x）中，其中0.42 < 为了获得介电常数同时将介电损耗保持在较低值，同时控制介电常数的温度特性，即谐振频率的温度特性。

公开(公告)号：US4749665A

公开(公告)日：1988-06-07

申请号：US919903

申请日：1986-10-16

申请人： Shinsuke Yano ,  Susumu Nishigaki

发明人： Shinsuke Yano ,  Susumu Nishigaki

IPC分类号： C04B35/10 ,  C03C10/00 ,  C04B35/111 ,  H05K1/03 ,  C03C14/00 ,  C03C8/14 ,  C03C8/24

CPC分类号： C04B35/111 ,  C03C10/0045 ,  C03C10/0054 ,  H05K1/0306

摘要： Partially crystallized ceramic articles is prepared by firing at low temperatures of 800.degree. to 1100.degree. C., a mixture consisting essentially of, (a) 40 to 50 wt. % of powdered, noncrystalline glass consisting essentially of 10 to 55 wt. % of at least one selected from the group consisting of CaO and MgO, 45 to 70 wt. % of SiO.sub.2, 0 to 30 wt. % of Al.sub.2 O.sub.3, 0 to 30% of B.sub.2 O.sub.3 and up to 10% impurities, the powder size of said glass being at least 4.0 m.sup.2 /g in terms of specific surface area measured by the BET Method; and (b) 60 to 50 wt. % of powdered Al.sub.2 O.sub.3 and the ceramic article is composed essentially of a noncrystallized glass phase, alumina and at least one of crystallized glass phase among anorthite, wollastonite, cordierite and mullite formed by partially crystallizing the glass (a). The ceramic articles exhibit a very high flexural strength well comparable with alumina substrate, together with greatly improved dielectric constant and thermal expansion and thus are especially useful in making multi-layer ceramic substrates for electronic applications.

摘要翻译： 部分结晶的陶瓷制品通过在800至1100℃的低温下烧制而制备，其混合物基本上由（a）40至50wt。 ％的粉末状非结晶玻璃基本上由10〜55重量％ ％为选自CaO和MgO的至少一种，45〜70重量％ ％的SiO 2，0〜30wt。 ％的Al2O3，0〜30％的B2O3和至多10％的杂质，所述玻璃的粉末尺寸以BET法测得的比表面积为至少4.0m 2 / g; 和（b）60至50wt。 Al2O3粉末和陶瓷制品基本上由非结晶玻璃相，氧化铝和通过部分结晶玻璃（a）形成的钙长石，硅灰石，堇青石和莫来石中的结晶玻璃相中的至少一种组成。 陶瓷制品表现出与氧化铝基底相当的非常高的弯曲强度，以及大大改善的介电常数和热膨胀，因此特别可用于制造用于电子应用的多层陶瓷基板。

公开(公告)号：US4748085A

公开(公告)日：1988-05-31

申请号：US931697

申请日：1986-11-14

申请人： Junzo Fukuda ,  Masashi Fukaya ,  Hiroshi Kawabe ,  Susumu Nishigaki

发明人： Junzo Fukuda ,  Masashi Fukaya ,  Hiroshi Kawabe ,  Susumu Nishigaki

IPC分类号： C04B35/111 ,  H01L21/48 ,  H01L23/15 ,  H05K1/00 ,  H05K1/03 ,  B32B15/00 ,  C03C8/14 ,  C03C8/24

CPC分类号： H01L21/481 ,  C04B35/111 ,  H01L23/15 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4629 ,  H05K3/4676 ,  Y10S428/901

摘要： In a multilayer ceramic circuit board comprising a substrate, an insulating layer on the substrate, and a conductive pattern on the insulating layer, an additive of Cr.sub.2 O.sub.3 or MnO.sub.2 is added to the insulating layer to reinforce adhesion between the insulating layer and the conductive pattern. Each of the substrate and the insulating layer is manufactured by firing at a temperature between 800.degree. C. and 1000.degree. C., alumina particles and a glass composition comprising an alumina component. When a total amount of alumina in the substrate is equal to or greater than that in the insulating layer, an amount of Cr.sub.2 O.sub.3 or MnO.sub.2 is restricted to a range between 0.1% and 10.0% by weight, with a difference between the total amounts of alumina falling within a range between 0% and 30% by weight. When the total amount of alumina in the substrate is smaller than that in the insulating layer, the amounts of Cr.sub.2 O.sub.3 and MnO.sub.2 may be between 0.1% and 10.0% by weight and between 0.1% and 15% by weight, respectively. The difference between the total amounts of alumina may be between 0% and 20% by weight.

摘要翻译： 在包括基板，基板上的绝缘层和绝缘层上的导电图案的多层陶瓷电路板中，将Cr 2 O 3或MnO 2的添加剂添加到绝缘层中以增强绝缘层和导电图案之间的粘附性。 基板和绝缘层中的每一个通过在800℃至1000℃的温度下煅烧，氧化铝颗粒和包含氧化铝组分的玻璃组合物来制造。 当基材中的氧化铝总量等于或大于绝缘层中的氧化铝的总量时，Cr 2 O 3或MnO 2的量被限制在0.1重量％至10.0重量％的范围内，氧化铝的总量之间的差异 在0％至30％之间的范围内。 当基板中的氧化铝的总量小于绝缘层中的氧化铝的总量时，Cr 2 O 3和MnO 2的量可以分别在0.1重量％至10.0重量％和0.1重量％至15重量％之间。 氧化铝的总量之间的差可以在0重量％至20重量％之间。

公开(公告)号：US4527010A

公开(公告)日：1985-07-02

申请号：US403443

申请日：1982-07-30

申请人： Shinzo Anazawa ,  Hitoshi Yamada ,  Kuniharu Noda ,  Yasuyuki Fujimoto

发明人： Shinzo Anazawa ,  Hitoshi Yamada ,  Kuniharu Noda ,  Yasuyuki Fujimoto

IPC分类号： H01L23/12 ,  H01L23/047 ,  H01L23/498 ,  H05K5/06

CPC分类号： H01L23/047 ,  H01L23/49844 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/16195 ,  H01L2924/30107 ,  H01L2924/3025

摘要： An electronic part mounting construction, such as a transistor package or a substrate for a resin mold device, has a substrate for mounting an electronic part on a principal surface, at least one metallized layer deposited on the principal surface and soldered to the electronic part thereon, another metallized layer continuously extended from the at least one metallized layer in a direction perpendicular thereto, and an insulator layer deposited on the other metallized layer. The other metallized layer is provided on a side surface of a wall member or the substrate. The other metallized layer and the insulator layer may be formed by steps of forming a hole in an insulator sheet, depositing a metallized layer and an insulator layer successively on the surface of the hole, and leaving the metallized layer and the insulator layer at predetermined region(s) by punching the insulator sheet.

摘要翻译： 诸如晶体管封装或用于树脂模具装置的基板的电子部件安装结构具有用于将电子部件安装在主表面上的基板，沉积在主表面上的至少一个金属化层并焊接到其上的电子部件上 ，在与其垂直的方向从所述至少一个金属化层连续延伸的另一金属化层和沉积在另一金属化层上的绝缘体层。 另一个金属化层设置在壁构件或基板的侧表面上。 另一个金属化层和绝缘体层可以通过以下步骤形成：在绝缘片上形成孔，在孔的表面上依次沉积金属化层和绝缘体层，并将金属化层和绝缘体层留在预定区域 通过冲压绝缘片。

公开(公告)号：US4472333A

公开(公告)日：1984-09-18

申请号：US307062

申请日：1981-09-30

申请人： Hiroshi Ohtani

发明人： Hiroshi Ohtani

IPC分类号： H01L23/00 ,  H01L23/13 ,  C04B33/32

CPC分类号： H01L23/562 ,  H01L23/13 ,  H01L2924/0002

摘要： A ceramic substrate for use as a semiconductor package which includes a plate member having an engraved cavity portion on a first face portion thereof and having a rounded corner on a peripheral surface opposite the first face portion and having a first and second stepped crest formed along the edge formed at the boundary of a second face portion opposite said first face portion for increasing impact resistance to chipping and cracking of the ceramic substrate. A method of manufacturing the ceramic substrate includes adding the ceramic powder to a first mold member, pressing a force applying member into the first mold member, forming on the ceramic substrate a first and second stepped crest, sintering the ceramic substrate and grinding at least one of the first and second stepped crests so as to round the at least one of the stepped crests.

摘要翻译： 一种用作半导体封装的陶瓷衬底，其包括在第一面部分上具有雕刻空腔部分的板构件，并且在与第一面部相对的圆周表面上具有圆角，并且具有沿着第一面部形成的第一和第二阶梯形顶部 边缘形成在与所述第一面部分相对的第二面部分的边界处，以增加对陶瓷基底的切屑和破裂的抗冲击性。 陶瓷基板的制造方法包括将陶瓷粉末添加到第一模具部件中，将施力部件压入第一模具部件，在陶瓷基板上形成第一和第二台阶状台阶，烧结陶瓷基板，研磨至少一个 的第一和第二阶梯形波峰，以使所述至少一个所述台阶波峰圆周。

公开(公告)号：US4165226A

公开(公告)日：1979-08-21

申请号：US891176

申请日：1978-03-29

申请人： Katsuhiko Kita

发明人： Katsuhiko Kita

IPC分类号： H01L21/50 ,  H01L23/057 ,  C03C27/00

CPC分类号： H01L23/057 ,  H01L21/50 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/09701

摘要： An element of a dual-in-line ceramic package such as a substrate or cover provided with a layer of sealing glass is prepared by forming powdered low-melting sealing glass into a shape conforming to that of the element, compressing and sintering the shaped powdered glass to form a solid sintered sealing glass preform, applying the preform to the surface of the element, and fusing it thereto by heating the assembly.

摘要翻译： 通过将粉末状低熔点密封玻璃形成为符合元件的形状，压制和烧结成形的粉末状的粉末，制备诸如具有密封玻璃层的衬底或盖的双列直插陶瓷封装的元件 玻璃以形成固体烧结的密封玻璃预制件，将预制件应用于元件的表面，并通过加热组件将其熔合到其上。