公开(公告)号：US6038173A

公开(公告)日：2000-03-14

申请号：US59081

申请日：1998-04-13

申请人： Emilio Miguel Yero

发明人： Emilio Miguel Yero

IPC分类号： G11C7/12 ,  G11C7/14 ,  G11C16/28 ,  G11C16/06

CPC分类号： G11C7/12 ,  G11C16/28 ,  G11C7/14

摘要： A memory read circuit includes a dynamically controlled precharging device that can be applied in the field of non-volatile (EEPROM, Flash EPROM) memories. The precharging circuit interrupts the precharging of the bit line and the reference line when the potential of the these lines reaches a boundary value referenced with respect to ground.

摘要翻译： 存储器读取电路包括可应用于非易失性存储器（EEPROM，闪存EPROM）存储器的动态控制的预充电器件。 当这些线的电位达到相对于地面参考的边界值时，预充电电路中断位线和参考线的预充电。

公开(公告)号：US6035385A

公开(公告)日：2000-03-07

申请号：US636634

申请日：1996-04-23

申请人： Maurice Le Van Suu

发明人： Maurice Le Van Suu

IPC分类号： G06F15/16 ,  G06F9/44 ,  G06F9/445 ,  G06F12/02 ,  G06F15/177 ,  G06F15/78 ,  G06N7/02 ,  G06N7/04

CPC分类号： G06F9/4403 ,  G06F15/7814 ,  G06N7/04

摘要： To enable the putting into use of a monolithic integrated circuit comprising a processor and a fuzzy logic coprocessor, both having a single program memory in common, an operation is effected by which, at the time of the initializing of the integrated circuit, a volatile, random-access memory of the coprocessor is loaded with instructions stored in this single program memory.

摘要翻译： 为了实现包括具有共同的单个程序存储器的处理器和模糊逻辑协处理器的单片集成电路，实现了在集成电路的初始化时易失性的， 协处理器的随机存取存储器被加载存储在该单个程序存储器中的指令。

公开(公告)号：US6035317A

公开(公告)日：2000-03-07

申请号：US4375

申请日：1998-01-08

申请人： Monier Guy

发明人： Monier Guy

IPC分类号： G06F7/52 ,  G06F7/72 ,  G06F7/00

CPC分类号： G06F7/5272 ,  G06F7/728 ,  G06F2207/382

摘要： A coprocessor including a first multiplication circuit and a second multiplication circuit with a series input to receive n bits and a series output to give n+k bits. The coprocesser also includes addition and multiplexing circuits enabling the data elements produced by the multiplication circuits to be added up with one another and with other data elements encoded on n bits. The invention makes parallel use of the multiplication circuits to carry out modular or non-modular operations on pieces of binary data having n bits or more.

公开(公告)号：US6034381A

公开(公告)日：2000-03-07

申请号：US871734

申请日：1997-06-09

申请人： Robert Pezzani

发明人： Robert Pezzani

IPC分类号： H01L21/332 ,  H01L29/74 ,  H01L29/747 ,  H03K17/72

CPC分类号： H01L29/7404 ,  H01L29/747

摘要： The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.

公开(公告)号：US6031475A

公开(公告)日：2000-02-29

申请号：US73495

申请日：1998-05-06

申请人： Michel Combe ,  Christian Fraisse

发明人： Michel Combe ,  Christian Fraisse

IPC分类号： H03M3/02 ,  H04B14/06 ,  H03M3/00

CPC分类号： H04B14/062

摘要： The present invention relates to a method and a device of information transfer between two circuits exchanging data via delta-sigma converters. The present invention includes coding the information in the form of at least one signal of determined frequency corresponding to an integer multiple of a frequency of the digital data samples; mixing, at a first end of a line carrying an oversampled digital signal of the converter, the signal of determined frequency; extracting from the mixture, at a second end of the line, the signal of determined frequency; and decoding the corresponding information.

摘要翻译： 本发明涉及通过delta-sigma转换器交换数据的两个电路之间的信息传送的方法和装置。 本发明包括以与数字数据样本的频率的整数倍对应的确定频率的至少一个信号的形式对信息进行编码; 在承载转换器的过采样数字信号的线路的第一端处混合确定频率的信号; 从混合物中提取线路的第二端，确定频率的信号; 并解码相应的信息。

公开(公告)号：US6025876A

公开(公告)日：2000-02-15

申请号：US663026

申请日：1996-06-07

申请人： Richard Bramley

发明人： Richard Bramley

IPC分类号： H04N5/93 ,  G06T9/00 ,  H04N7/26 ,  H04N7/30

CPC分类号： G06T9/007 ,  H03M13/05 ,  H03M5/145

摘要： A device for decoding a data stream representing moving pictures encoded according to the MPEG standard in which a logical unit receives from an offset stage data containing the maximum number of bits in a variable length code returns the length of each decoded code to the offset stage, and produces a decoded value of each code. The logical unit includes a controller which controls at least two separate processing units, of which a first processing unit extracts the code length and addresses it to the offset stage, and a second processing unit decodes the codes.

摘要翻译： 用于解码表示根据MPEG标准编码的运动图像的数据流的装置，其中逻辑单元从偏移级接收到包含可变长度码中的最大位数的数据，将每个解码码的长度返回到偏移级， 并产生每个代码的解码值。 逻辑单元包括控制器，其控制至少两个单独的处理单元，其中第一处理单元提取代码长度并将其寻址到偏移级，并且第二处理单元对代码进行解码。

公开(公告)号：US6017778A

公开(公告)日：2000-01-25

申请号：US971850

申请日：1997-11-17

申请人： Robert Pezzani

发明人： Robert Pezzani

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/822 ,  H01L21/8222 ,  H01L23/40 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H05K7/20 ,  H01L21/332

CPC分类号： H01L21/761 ,  H01L27/08 ,  H01L27/0814

摘要： A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

摘要翻译： 单片组件包括在第一导电类型的低掺杂半导体晶片的整个厚度上形成的垂直功率半导体元件，其底表面均匀地涂覆有金属化。 这些部件中的至少一些，所谓的自主部件，形成在基板的绝缘部分中，其侧面绝缘由第二导电类型的扩散壁提供，并且其底部通过插入在底表面 的基底和金属化。

公开(公告)号：US6011724A

公开(公告)日：2000-01-04

申请号：US980195

申请日：1997-11-26

申请人： Alessandro Brigati ,  Jean Devin ,  Bruno LeConte

发明人： Alessandro Brigati ,  Jean Devin ,  Bruno LeConte

IPC分类号： G11C16/16 ,  G11C16/30 ,  G11C11/34

CPC分类号： G11C16/30 ,  G11C16/16 ,  H02M2001/0025

摘要： A method for the erasure of a non-volatile and electrically erasable memory in which the amplitude of the pulses that are sent to erase the memory varies as a function of the number of pulses previously sent. A circuit for the generation of erasure pulses of variable amplitude for a non-volatile and electrically erasable memory.

摘要翻译： 用于擦除非易失性和电可擦除存储器的方法，其中发送到擦除存储器的脉冲的幅度随先前发送的脉冲数的函数而变化。 用于产生用于非易失性和电可擦除存储器的可变幅度的擦除脉冲的电路。

公开(公告)号：US5998813A

公开(公告)日：1999-12-07

申请号：US780723

申请日：1997-01-08

申请人： Eric Bernier

发明人： Eric Bernier

IPC分类号： H01L29/74 ,  H01L21/332 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L29/747 ,  H01L31/111

CPC分类号： H01L27/0248

摘要： A monolithic component for protection against over-currents liable to occur on a line in series with which is connected a detection resistor, comprises a first cathode-gate thyristor associated with an avalanche diode and a second anode-gate thyristor of the gate triggering type or forward breakover type, its breakover voltage being substantially equal to the avalanche voltage of the avalanche diode.

摘要翻译： 用于防止易于发生在与检测电阻器连接的线路上的过电流的单片部件包括与雪崩二极管相关联的第一阴极栅极晶闸管和栅极触发类型的第二阳极 - 栅极晶闸管， 正向断流型，其击穿电压基本上等于雪崩二极管的雪崩电压。

公开(公告)号：US5995395A

公开(公告)日：1999-11-30

申请号：US835048

申请日：1997-03-27

申请人： Bertrand Rivet

发明人： Bertrand Rivet

IPC分类号： H02M1/08 ,  H02M7/12 ,  H02M7/155 ,  H02M7/162 ,  H03K17/13

CPC分类号： H03K17/136 ,  H02M7/125 ,  H02M7/1623

摘要： The present invention relates to a device for controlling a composite bridge including two anode-gate thyristors, the cathodes of which are connected together to a positive output terminal, the gates of the two thyristors being interconnected. The device includes a single-throw switch, controllable to be turned off and on, connected on the one hand to the two thyristors and on the other hand to a reference potential, and control means to turn on the switch only in a predetermined voltage range around the zero voltage of an a.c. voltage of the composite bridge.

摘要翻译： 本发明涉及一种用于控制复合电桥的装置，其中包括两个阳极栅极晶闸管，其阴极连接在一起为正输出端，两个晶闸管的栅极相互连接。 该装置包括可控制地关断和接通的单掷开关，一方面连接到两个晶闸管，另一方面连接到参考电位;以及控制装置，仅在预定电压范围内接通开关 围绕交流的零电压 复合桥电压。