公开(公告)号：US20140062545A1

公开(公告)日：2014-03-06

申请号：US13602215

申请日：2012-09-03

Applicant: Dai Dai

Inventor： Dai Dai

IPC: H03L7/00

CPC classification number: H03M1/0818 ,  H03M1/365

Abstract: The core concept of this ADC is the high-speed fully-differential comparators which are clocked at 2.64 GHz and used in a 60 GHz transceiver. The comparator consists of a pre-amplifier stage, a capture stage, a regeneration cell and an output latch. The pre-amplifier stage is not clocked; therefore, the pre-amplifier stage does not suffer initialization and transient behavior effects when the clock signal switches state. The transient response of being enabled and disabled is eliminated. Instead, a capture stage transfers the contents of the pre-amplifier stage into a memory regeneration stage. The capture stage is clocked by pulses that are timed to minimize the clock kick-back generated by the memory regeneration stage. The clock kick-back is reduced even when many comparators are coupled to the PGA. The comparators, instead of having extra dummy fingers, are also aligned right next to each other to minimize the mismatching layout effect.

Abstract translation: 该ADC的核心概念是高速全差分比较器，时钟频率为2.64 GHz，用于60 GHz收发器。 比较器由前置放大器级，捕获级，再生单元和输出锁存器构成。 前置放大器级没有计时; 因此，当时钟信号切换状态时，前置放大器级不会受到初始化和瞬态特性的影响。 消除了启用和禁用的瞬态响应。 相反，捕获级将前置放大器级的内容传送到存储器再生级。 捕获级由定时的脉冲计时，以最小化由存储器再生阶段产生的时钟反冲。 即使许多比较器耦合到PGA，时钟反转也减少。 比较器而不是具有额外的虚拟手指，也彼此对准，以最小化不匹配的布局效果。

公开(公告)号：US08638252B2

公开(公告)日：2014-01-28

申请号：US13306982

申请日：2011-11-30

Applicant: Mahdi Davoodabadi

Inventor： Mahdi Davoodabadi

IPC: H03M1/16

CPC classification number: H03M1/002 ,  H03M1/146 ,  H03M1/365

Abstract: An analog-to-digital converter comprises a first set of comparators configured for generating a coarse digital measurement of an analog input signal, and a second set of comparators for performing a fine digital measurement of the analog input signal. The second set comprises a plurality of dynamic comparators, wherein each dynamic comparator is configurable for being activated by a clock signal. An activation circuit processes the coarse measurement and an input clock signal for generating a set of activation signals, which activate a subset of the dynamic comparators to generate the fine digital measurement.

Abstract translation: 模数转换器包括被配置用于产生模拟输入信号的粗略数字测量的第一组比较器和用于执行模拟输入信号的精细数字测量的第二组比较器。 第二组包括多个动态比较器，其中每个动态比较器可配置为由时钟信号激活。 激活电路处理粗略测量和输入时钟信号以产生一组激活信号，其激活动态比较器的子集以产生精细数字测量。

公开(公告)号：US07352806B2

公开(公告)日：2008-04-01

申请号：US10811223

申请日：2004-03-26

Applicant: Ismail Lakkis

Inventor： Ismail Lakkis

IPC: H03K5/159 ,  H04K1/10

CPC classification number: H04L1/0618 ,  H04J13/16 ,  H04L1/0003 ,  H04L1/0059 ,  H04L27/2601

Abstract: A method of communicating over a wideband communication channel divided into a plurality of sub-channels comprises dividing a single serial message intended for one of the plurality of communication devices into a plurality of parallel messages, encoding each of the plurality of parallel messages onto at least some of the plurality of sub-channels, and transmitting the encoded plurality of parallel messages to the communication device over the wideband communication channel.

Abstract translation: 一种通过划分成多个子信道的宽带通信信道进行通信的方法包括将用于多个通信设备之一的单个串行消息划分为多个并行消息，至少将多个并行消息中的每一个编码至少 多个子信道中的一些，并且通过宽带通信信道将经编码的多个并行消息发送到通信设备。

公开(公告)号：US10734957B2

公开(公告)日：2020-08-04

申请号：US16352575

申请日：2019-03-13

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  Kevin Jing ,  Steve Gao

IPC: H03G5/28 ,  H03H11/12 ,  H03G1/00 ,  H03F3/45

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：US10277182B2

公开(公告)日：2019-04-30

申请号：US15833458

申请日：2017-12-06

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  Kevin Jing ,  Steve Gao

IPC: H03G1/00 ,  H03H11/12 ,  H03F3/45 ,  H03G5/28

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：US09793885B2

公开(公告)日：2017-10-17

申请号：US15340430

申请日：2016-11-01

Applicant: Tensorcom, Inc.

Inventor： Dai Dai

IPC: H03M1/34 ,  H03K5/24 ,  H03H11/48 ,  H03M1/00 ,  H03M1/08 ,  H03M1/18

CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier.

公开(公告)号：US09793880B2

公开(公告)日：2017-10-17

申请号：US14828955

申请日：2015-08-18

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  KhongMeng Tham

IPC: H03K3/012 ,  H01Q1/50 ,  H03K17/56 ,  G05F3/16 ,  H04B5/00

CPC classification number: H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

公开(公告)号：US09478873B2

公开(公告)日：2016-10-25

申请号：US14641968

申请日：2015-03-09

Applicant: Tensorcom, Inc.

Inventor： Joel Abe Balbien ,  HungYu David Yang ,  Thaddeus John Gabara

IPC: H04B7/02 ,  H01Q21/29 ,  H01Q1/12 ,  H01Q1/24 ,  H01Q1/38 ,  H01Q1/52 ,  H01Q3/24 ,  H01Q9/16 ,  H01Q21/28 ,  H01Q25/00 ,  H01Q3/04 ,  H04B1/04

CPC classification number: H01Q21/293 ,  H01Q1/1257 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/525 ,  H01Q3/04 ,  H01Q3/242 ,  H01Q9/16 ,  H01Q21/28 ,  H01Q25/00 ,  H01Q25/005 ,  H04B7/024

Abstract: A portable unit with an endfire antenna and operating at 60 GHz makes an optimum communication channel with an endfire antenna in an array of antennas distributed over the area of a ceiling. The portable unit is pointed towards the ceiling and the system controlling the ceiling units selects and adjusts the positioning of an endfire antenna mounted on a 3-D adjustable rotatable unit. Several transceivers can be mounted together, offset from one another, to provide a wide coverage in both azimuth direction and elevation direction. These units can be rigidly mounted as an array in a ceiling, apparatus. The system controlling the ceiling array selects one of the transceivers in one of the units to make the optimum communication channel to the portable unit. The system includes the integration of power management features by switching between Wi-Fi in favor of the 60 GHz channel.

Abstract translation: 具有端射天线并以60GHz操作的便携式单元与分布在天花板区域上的天线阵列中的端射天线形成最佳通信信道。 便携式设备被指向天花板，并且控制天花板单元的系统选择并调节安装在3-D可调节可旋转单元上的端面天线的定位。 几个收发器可以一起安装在一起，彼此偏移，以便在方位方向和仰角方向上提供广泛的覆盖。 这些单元可以作为阵列刚性地安装在天花板，装置中。 控制天花板阵列的系统选择其中一个单元中的一个收发器，以将便携式单元的最佳通信信道。 该系统包括通过在支持60 GHz频道的Wi-Fi之间切换来集成电源管理功能。

公开(公告)号：US20160173131A1

公开(公告)日：2016-06-16

申请号：US15011252

申请日：2016-01-29

Applicant: Tensorcom, Inc.

Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

IPC: H03M13/11

CPC classification number: H03M13/1145 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/1148 ,  H03M13/116

Abstract: Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

Abstract translation: 处理器被布置在流水线结构中以在多层数据上操作，每层包括多组数据。 存储器的输入耦合到流水线中的最后一个处理器的输出，并且存储器的输出耦合到流水线中的第一处理器的输入。 在流水线中执行多路复用和解复用操作。 对于每个层中的每个组，将从存储器读取的存储结果应用于流水线结构中的第一处理器。 存储结果的计算结果在最后一个处理器处输出并存储在存储器中。 一旦对第一层中的最后一组数据的处理完成，相应的处理器被配置为在管线完成对第一层的处理之前处理下一层中的数据。 从下一层获得的存储结果包括从第一层之前的层产生的计算结果。

公开(公告)号：US09143204B2

公开(公告)日：2015-09-22

申请号：US13163562

申请日：2011-06-17

Applicant: KhongMeng Tham ,  Zaw Soe

Inventor： KhongMeng Tham ,  Zaw Soe

IPC: H03G3/10 ,  H04B5/00 ,  G05F3/16

CPC classification number: H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

Abstract translation: 当设计高频（〜60GHz）电路时，本发明消除了对“电容器耦合”或“变压器耦合”的需求以及与这些耦合技术相关联的不期望的寄生电容和电感。 在这个频率下，两个相邻阶段之间的距离需要最小化。 与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。 该谐振电路的引入允许使用金属迹线将第一级“直接耦合”到下一级。 “直接耦合”技术将高频信号和偏置电压都通过下一级。 与“交流耦合”或“变压器耦合”方法相比，“直接耦合”方法克服了大的管芯面积使用，因为既不需要电容器也不需要变压器来在级之间传输高频信号。