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公开(公告)号：US20180144435A1
公开(公告)日：2018-05-24
申请号：US15360057
申请日：2016-11-23
发明人： Jiasheng Chen , Timour Paltashev , Alexander Lyashevsky , Carl Kittredge Wakeland , Michael J. Mantor
CPC分类号： G06T1/20 , G06F9/3887 , G06F9/542 , G06F2009/3883 , G06F2209/548 , G06T1/60
摘要： Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.
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公开(公告)号：US09846581B2
公开(公告)日：2017-12-19
申请号：US14480556
申请日：2014-09-08
发明人： Tao Huang , Yiqun Ge , Qifan Zhang , Wuxian Shi , Wen Tong
CPC分类号： G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
摘要： A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.
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13.发明申请公开(公告)号：US20150074445A1
公开(公告)日：2015-03-12
申请号：US14480522
申请日：2014-09-08
发明人： Tao Huang , Qifan Zhang , Wuxian Shi , Yiqun Ge , Wen Tong
CPC分类号： G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
摘要： A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.
摘要翻译： 具有多个流水线处理级的无时钟异步处理电路或系统利用自定时发生器来调整每个处理阶段所需的延迟以完成处理周期。 因为不同的处理阶段可能需要不同的时间量来完成处理，或者可能需要根据特定阶段所需的处理而产生不同的延迟，所以自定时发生器可以被调谐到每个阶段的必要延迟或者可以被编程地配置。
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公开(公告)号：US07884743B2
公开(公告)日：2011-02-08
申请号：US12431828
申请日：2009-04-29
IPC分类号： H03M7/00
CPC分类号： H03M7/4006 , G06F9/30018 , G06F2009/3883 , H04N19/44 , H04N19/91
摘要： Disclosed herein is an arithmetic decoding device including: an arithmetic decoding unit configured to decode coded data resulting from arithmetic coding on a basis of a context variable indicating a probability state and a most probable symbol; a plurality of arithmetic registers configured to supply the context variable to the arithmetic decoding unit and retain a result of operation by the arithmetic decoding unit; and a plurality of save registers configured to save contents retained in the arithmetic registers.
摘要翻译： 本文公开了一种算术解码装置，包括：算术解码单元，被配置为基于指示概率状态的上下文变量和最可能的符号来解码由算术编码产生的编码数据; 多个算术寄存器，被配置为将所述上下文变量提供给所述算术解码单元，并且保留所述算术解码单元的操作结果; 以及多个保存寄存器，被配置为保存保留在算术寄存器中的内容。
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公开(公告)号：US20240248750A1
公开(公告)日：2024-07-25
申请号：US18626000
申请日：2024-04-03
发明人： Wei Shao , Christopher Wilson , Damien McNamara
CPC分类号： G06F9/4843 , G06F9/30043 , G06F9/3877 , G06F11/1004 , G06F11/1497 , G06F11/1641 , G06F21/6245 , G06F21/64 , G06F2009/3883
摘要： A graphics processing system for operation with a data store includes processing units for processing tasks. A check unit forms a signature which is characteristic of an output from processing a task on a processing unit, and a fault detection unit compares signatures formed at the check unit. The graphics processing system processes each task first and second times at the processing units so as to generate first and second processed outputs. The graphics processing system write outs the first processed output to the data store, reads back the first processed output from the data store and forms at the check unit a first signature characteristic of the first processed output as read back from the data store; forms at the check unit a second signature characteristic of the second processed output, compares the first and second signatures at the fault detection unit, and raises a fault signal if the signatures do not match.
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公开(公告)号：US11977913B2
公开(公告)日：2024-05-07
申请号：US17867635
申请日：2022-07-18
发明人： Wei Shao , Christopher Wilson , Damien McNamara
CPC分类号： G06F9/4843 , G06F9/30043 , G06F9/3877 , G06F11/1004 , G06F11/1497 , G06F11/1641 , G06F21/6245 , G06F21/64 , G06F2009/3883
摘要： A graphics processing system for operation with a data store, comprising: one or more processing units for processing tasks; a check unit operable to form a signature which is characteristic of an output from processing a task on a processing unit; and a fault detection unit operable to compare signatures formed at the check unit; wherein the graphics processing system is operable to process each task first and second times at the one or more processing units so as to, respectively, generate first and second processed outputs, the graphics processing system being configured to: write out the first processed output to the data store; read back the first processed output from the data store and form at the check unit a first signature which is characteristic of the first processed output as read back from the data store; form at the check unit a second signature which is characteristic of the second processed output; compare the first and second signatures at the fault detection unit; and raise a fault signal if the first and second signatures do not match.
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17.发明授权公开(公告)号：US11886878B2
公开(公告)日：2024-01-30
申请号：US16712891
申请日：2019-12-12
发明人： Sukesh Shenoy , Adam N. C. Clark , Indrani Paul
IPC分类号： G06F1/00 , G06F9/30 , G06F9/48 , G06F1/3203 , G06F9/38
CPC分类号： G06F9/30083 , G06F1/3203 , G06F9/3877 , G06F9/4843 , G06F2009/3883
摘要： An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.
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公开(公告)号：US09606801B2
公开(公告)日：2017-03-28
申请号：US14480531
申请日：2014-09-08
发明人： Wen Tong , Yiqun Ge , Qifan Zhang , Wuxian Shi , Tao Huang
CPC分类号： G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
摘要： A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.
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19.发明授权公开(公告)号：US09489200B2
公开(公告)日：2016-11-08
申请号：US14480491
申请日：2014-09-08
发明人： Tao Huang , Qifan Zhang , Wuxian Shi , Yiqun Ge , Wen Tong
CPC分类号： G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
摘要： A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.
摘要翻译： 无时钟异步处理电路或系统被配置为以多种模式操作。 在初始化模式（例如，复位，初始化，启动）中，与异步电路相关联的自定时发生器被配置为在接收到触发之后的第一时间段内产生有效完成信号（锁存输出处理的数据） 信号。 在正常模式下，自定时发生器被配置为在接收到触发信号之后的第二时间段内产生有效完成信号。 在一个实施例中，在初始化模式期间，异步电路比正常模式下的锁存输出慢。
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公开(公告)号：US20150169328A1
公开(公告)日：2015-06-18
申请号：US14310283
申请日：2014-06-20
IPC分类号： G06F9/38
CPC分类号： G06F9/3877 , G06F9/3879 , G06F9/4881 , G06F9/547 , G06F15/7889 , G06F2009/3883 , G06F2209/543
摘要： When a main processor issues a command to co-processor, a timeout value is included in the command. As the co-processor attempts to execute the command, it is determined whether the attempt is taking time beyond what is permitted by the timeout value. If the timeout is exceeded then responsive action is taken, such as the generation of a command timeout type failure message. The receipt of the command with the timeout value, and the consequent determination of a timeout condition for the command, may be determined by: the co-processor that receives the command, or a watchdog timer that is separate from the co-processor. Also, detection of co-processor hang and/or hung co-processor conditions during the time that a co-processor is executing a command for the main processor.
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