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    Method for realizing a neural network
    11.
    发明授权
    Method for realizing a neural network 有权

    公开(公告)号：US11704561B2

    公开(公告)日：2023-07-18

    申请号：US16955356

    申请日：2018-12-12

    Applicant: Siemens Aktiengesellschaft

    Inventor： Thomas Hinterstoisser ,  Martin Matschnig ,  Herbert Taucher

    IPC: G06F30/323 ,  G06F30/327 ,  G06N3/08 ,  G06N3/063

    CPC classification number: G06N3/08 ,  G06F30/323 ,  G06F30/327 ,  G06N3/063

    Abstract: A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.

    DYNAMIC ABSTRACT GENERATION AND SYNTHESIS FLOW WITH AREA PREDICTION
    12.
    发明公开
    DYNAMIC ABSTRACT GENERATION AND SYNTHESIS FLOW WITH AREA PREDICTION 审中-公开

    公开(公告)号：US20230214563A1

    公开(公告)日：2023-07-06

    申请号：US17567328

    申请日：2022-01-03

    Applicant: International Business Machines Corporation

    Inventor： Daniel Lewis ,  Rahul M Rao

    IPC: G06F30/327 ,  G06F30/39 ,  G06F30/323

    CPC classification number: G06F30/327 ,  G06F30/39 ,  G06F30/323

    Abstract: A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

    Verification of hardware design for data transformation pipeline
    14.
    发明授权
    Verification of hardware design for data transformation pipeline 有权

    公开(公告)号：US11663385B2

    公开(公告)日：2023-05-30

    申请号：US17478739

    申请日：2021-09-17

    Applicant: Imagination Technologies Limited

    Inventor： Sam Elliott

    IPC: G06F30/3323 ,  G06F30/367 ,  G06F30/398 ,  G06F30/3308 ,  G06F30/323 ,  G01R31/00 ,  G01R31/3183

    CPC classification number: G06F30/3323 ,  G01R31/318357 ,  G06F30/323 ,  G06F30/3308 ,  G06F30/367 ,  G06F30/398

    Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by replacing one or more of the data transformation elements in the hardware design with a function element which is treated as an unevaluated function of its combinational inputs by a formal verification tool such that during formal verification the function element will produce the same output for the same inputs, and formally verifying that for each transaction of a set of transactions an instantiation of the modified hardware design for the data transformation pipeline produces a set of one or more outputs that matches a reference set of one or more outputs for that transaction.

    Method, device, and storage medium for simulating a design
    15.
    发明授权
    Method, device, and storage medium for simulating a design 有权

    公开(公告)号：US11651130B2

    公开(公告)日：2023-05-16

    申请号：US17548110

    申请日：2021-12-10

    Applicant: XEPIC CORPORATION LIMITED

    Inventor： Jinya Zhang

    IPC: G06F30/30 ,  G06F30/3308 ,  G06F30/323

    CPC classification number: G06F30/3308 ,  G06F30/323

    Abstract: The present disclosure provides methods and devices for simulating a design, wherein the design comprises a main class with parameters and a plurality of instances of the main class, wherein the plurality of instances comprise a first instance and a second instance. The method includes: determining, by analyzing the design, a plurality of secondary classes associated with instantiating the main class, wherein the plurality of secondary classes are used as the parameters of the main class and comprise a first secondary class corresponding to the first instance and a second secondary class corresponding to the second instance; translating the design to generate a first temporary code associated with the plurality of instances; generating, based on the first temporary code, a plurality of instance machine codes corresponding to the plurality of instances; and simulating the design based on the plurality of instance machine codes.

    STANDARD CELL DESIGN
    17.
    发明公开
    STANDARD CELL DESIGN 审中-公开

    公开(公告)号：US20240362392A1

    公开(公告)日：2024-10-31

    申请号：US18769843

    申请日：2024-07-11

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

    IPC: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F111/20

    CPC classification number: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

    Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

    Standard cell design
    20.
    发明授权
    Standard cell design 有权

    公开(公告)号：US12073165B2

    公开(公告)日：2024-08-27

    申请号：US17476615

    申请日：2021-09-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

    IPC: G06F30/30 ,  G06F30/323 ,  G06F30/392 ,  G06F30/398 ,  G06F111/20

    CPC classification number: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

    Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

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