公开(公告)号：US12074200B2

公开(公告)日：2024-08-27

申请号：US18370626

申请日：2023-09-20

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Keiji Okumura

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/745 ,  H01L21/04 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/1095 ,  H01L29/083 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/745 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L21/0465 ,  H01L21/047 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696

Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

公开(公告)号：US20170178947A1

公开(公告)日：2017-06-22

申请号：US15452592

申请日：2017-03-07

Applicant: IXYS Corporation

Inventor： Elmar Wisotzki ,  Christoph Koerber

IPC: H01L21/761 ,  H01L21/762 ,  H01L21/78 ,  H01L29/08 ,  H01L29/745 ,  H01L29/06 ,  H01L21/763 ,  H01L21/223

CPC classification number: H01L21/761 ,  H01L21/223 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/763 ,  H01L21/768 ,  H01L21/78 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0646 ,  H01L29/0834 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/745 ,  H01L2224/056 ,  H01L2924/1301 ,  H01L2924/00014

Abstract: A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for example, 8500 volts) without suffering breakdown. A P type peripheral aluminum diffusion region extends around the bottom periphery of a thick die. The peripheral aluminum diffusion region extends upward from the bottom surface of the die, extending into N− type bulk silicon. A deep peripheral trench extends around the upper periphery of the die. The deep trench extends from the topside of the die down toward the peripheral aluminum diffusion region. A P type sidewall doped region extends laterally inward from the inner sidewall of the trench, and extends laterally outward from the outer sidewall of the trench. The P type sidewall doped region joins with the P type peripheral aluminum diffusion region, thereby forming a separation edge diffusion structure that surrounds the active area of the die.

公开(公告)号：US20170033208A1

公开(公告)日：2017-02-02

申请号：US15290377

申请日：2016-10-11

Applicant: ABB Schweiz AG

Inventor： Hendrik Ravener ,  Tobias Wikström ,  Hermann Amstutz ,  Norbert Meier

IPC: H01L29/745 ,  H01L23/31 ,  H01L21/56 ,  H01L29/45 ,  H01L29/66 ,  H01L23/051 ,  H01L29/74

CPC classification number: H01L29/745 ,  H01L21/565 ,  H01L23/051 ,  H01L23/3185 ,  H01L29/45 ,  H01L29/66363 ,  H01L29/7416 ,  H01L29/7424 ,  H01L29/744 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active region, a rubber ring as an edge passivation for the wafer and a gate ring placed on a ring-shaped gate contact on the termination region for contacting the gate electrodes of a thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring. The area consumed by the ring-shaped gate contact on the termination or edge region can be minimized. The upper surface of the gate ring and the upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer.

Abstract translation: 本发明涉及具有有源区和围绕有源区的端接区的晶片的截止功率半导体器件，作为晶片的边缘钝化的橡胶环和放置在环形栅极接触上的栅极环 在用于接触形成在晶片的有源区域中的晶闸管电池的栅电极的端接区域上。 在关断功率半导体器件中，门环的外周面与橡胶环接触以限定橡胶环的内边界。 可以使终端或边缘区域上的环状栅极接触消耗的面积最小化。 门环的上表面和橡胶环的上表面形成在与晶片的第一主侧平行的平面中延伸的连续表面。

公开(公告)号：US08519432B2

公开(公告)日：2013-08-27

申请号：US12079841

申请日：2008-03-27

Applicant: Jeffrey G. Barrow ,  Javier A. Salcedo ,  A. Paul Brokaw

Inventor： Jeffrey G. Barrow ,  Javier A. Salcedo ,  A. Paul Brokaw

IPC: H01L29/66

CPC classification number: H01L29/745 ,  H01L29/7408 ,  H01L29/7455

Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

Abstract translation: 半导体开关包括被布置为提供类SCR功能的PNPN结构，以及优选地集成在公共基板上的MOS栅极结构。 该开关包括用于MOS栅极的欧姆接触，以及用于PNPN结构的阴极和栅极区域; 阳极接触是固有的。 固定电压通常被施加到外部节点。 MOS栅极结构允许在导通时在外部节点和本征阳极之间传导电流，并且当适当的电压施加到栅极触点时，PNPN结构将电流从阳极传导到阴极。 再生反馈一旦开始进行，就保持开关状态。 MOS门禁止外部节点和阳极之间的电流流动，从而在关闭时关闭开关。 当导通时，MOS栅极的沟道电阻用作镇流电阻。

公开(公告)号：US20070114565A1

公开(公告)日：2007-05-24

申请号：US11285801

申请日：2005-11-23

Applicant: Udaysimha Makaram

Inventor： Udaysimha Makaram

IPC: H01L29/74

CPC classification number: H01L29/745

Abstract: An integrated FET-thyristor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type formed in the substrate proximate an upper surface of the substrate, and a second semiconductor region of the second conductivity type formed in the substrate proximate a bottom surface of the substrate. The second semiconductor region is substantially vertically aligned with and spaced apart from the first semiconductor region. A third semiconductor region of the first conductivity type is formed in a portion of the first semiconductor region proximate the upper surface of the substrate. At least one gate region of the second conductivity type is formed on a sidewall of the substrate and substantially surrounding at least a portion of each of the first, second and third semiconductor regions.

Abstract translation: 一种集成的FET-晶闸管器件包括：第一导电类型的半导体衬底，在衬底的上表面附近形成的第二导电类型的第一半导体区域，以及形成在衬底中的第二导电类型的第二半导体区域 衬底接近衬底的底表面。 第二半导体区域与第一半导体区域基本上垂直对准并与第一半导体区域间隔开。 第一导电类型的第三半导体区域形成在靠近衬底的上表面的第一半导体区域的一部分中。 第二导电类型的至少一个栅极区形成在衬底的侧壁上，并且基本上围绕第一，第二和第三半导体区域中的每一个的至少一部分。

公开(公告)号：US07221047B2

公开(公告)日：2007-05-22

申请号：US11241991

申请日：2005-10-04

Applicant: Kenji Oota ,  Futoshi Tokunoh

Inventor： Kenji Oota ,  Futoshi Tokunoh

IPC: H01L23/48

CPC classification number: H01L24/72 ,  H01L23/051 ,  H01L23/3185 ,  H01L29/745 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1′) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1a′).

Abstract translation: 在半导体衬底（1）的外周台阶部分（1'）上形成一个栅极电极（1a），以面对压接支承块（6），并且凸接触部分（1g）是 形成在栅电极的表面上的预定位置上以接触压力接触支撑块。 从内周到与凸接触部相邻的位置的栅电极的表面积被涂覆有绝缘膜（1d）。 凸形接触部分（1g）由与栅电极成一体或由另一个栅电极（1a'）形成的凸部形成。

公开(公告)号：US20040183093A1

公开(公告)日：2004-09-23

申请号：US10765158

申请日：2004-01-28

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Kenji Oota ,  Futoshi Tokunoh

IPC: H01L029/74

CPC classification number: H01L24/72 ,  H01L23/051 ,  H01L23/3185 ,  H01L29/745 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1null) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1anull).

Abstract translation: 在半导体基板（1）的外周台阶部（1'）上形成有与压接支承块（6）相对的栅电极（1a），在 在栅电极的表面上的预定位置，以接触压力接触支撑块。 从内周到与凸接触部相邻的位置的栅电极的表面积被涂覆有绝缘膜（1d）。 凸形接触部分（1g）由与栅电极成一体或由另一个栅电极（1a'）形成的凸部形成。

公开(公告)号：US06107649A

公开(公告)日：2000-08-22

申请号：US95481

申请日：1998-06-10

Applicant: Jian H. Zhao

Inventor： Jian H. Zhao

IPC: H01L29/16 ,  H01L29/24 ,  H01L29/739 ,  H01L29/745 ,  H01L29/78

CPC classification number: H01L29/1602 ,  H01L29/16 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/745 ,  H01L29/1608

Abstract: Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. A layer of the top surface forms a control layer. A semiconductor layer junction, remote from top and bottom device surfaces, forms a blocking p-n junction capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region extending from the top surface into the control layer. A conductive tub region, spaced apart from the top conductive region, extends from the top surface at least through the control layer. A field effect region is disposed in the control layer between the top conductive region and tub region. A gate contact is formed over the field effect region causing the creation and interruption of a conductive channel between the top conductive region and the conductive tub region so as to turn the device on and off. In one device embodiment, a separate latch-on gate overlying the conductive tub is provided for device turn-on.

Abstract translation: 功率半导体器件具有交替的p型和n型导电性以及顶部和底部器件表面的多个半导体层。 顶层的一层形成控制层。 远离顶部和底部器件表面的半导体层结形成能够维持施加的器件电压的阻挡p-n结。 顶部欧姆接触覆盖从顶表面延伸到控制层的顶部导电区域。 与顶部导电区域间隔开的导电槽区域至少通过控制层从顶表面延伸。 场效应区域设置在顶部导电区域和盆地区域之间的控制层中。 在场效应区域上形成栅极接触，导致在顶部导电区域和导电槽区域之间的导电通道的产生和中断，以便打开和关闭装置。 在一个器件实施例中，提供了覆盖导电槽的单独的锁定栅极用于器件导通。

公开(公告)号：US4636830A

公开(公告)日：1987-01-13

申请号：US667827

申请日：1984-11-02

Applicant: Jayant K. Bhagat

Inventor： Jayant K. Bhagat

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/745 ,  H01L29/749 ,  H01L29/72 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/7455 ,  H01L29/0684 ,  H01L29/1016 ,  H01L29/42308 ,  H01L29/745 ,  H01L29/749

Abstract: A new semiconductor power device, suitable for electrical switching in automotive applications, is proposed. This device combines the low specific on-resistance achievable with bipolar regenerative switching devices with the convenience of insulated gate control of not only turn-on but also turn-off. A device structure is presented that also includes a pinch resistance effect to more rapidly produce turn-off. The anode region of the device is electrically shorted to its contiguous N-type region.

Abstract translation: 提出了一种适用于汽车应用中的电气开关的新型半导体功率器件。 该器件将可实现的低比导通电阻与双极型再生开关器件相结合，不仅可以实现接通而且关断的绝缘栅极控制。 提出了一种装置结构，其还包括夹紧电阻效应以更快地产生关断。 器件的阳极区域与其邻接的N型区域电短路。

公开(公告)号：US4611235A

公开(公告)日：1986-09-09

申请号：US617106

申请日：1984-06-04

Applicant: Jayant K. Bhagat

Inventor： Jayant K. Bhagat

IPC: H01L29/74 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/745 ,  H01L29/749 ,  H01L29/72 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L29/745 ,  H01L29/0684 ,  H01L29/1016 ,  H01L29/42308 ,  H01L29/7455 ,  H01L29/749

Abstract: A new semiconductor power device, suitable for electrical switching in automotive applications, is proposed. This device combines the low specific on-resistance achievable with bipolar regenerative switching devices with the convenience of insulated gate control of not only turn-on but also turn-off. A device structure is presented that also includes a pinch resistance effect to more rapidly produce turn-off.

Abstract translation: 提出了一种适用于汽车应用中的电气开关的新型半导体功率器件。 该器件将可实现的低比导通电阻与双极型再生开关器件相结合，不仅可以实现接通而且关断的绝缘栅极控制。 提出了一种装置结构，其还包括夹紧电阻效应以更快地产生关断。