公开(公告)号：US09059042B2

公开(公告)日：2015-06-16

申请号：US14078979

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/78603

Abstract: One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.

Abstract translation: 所公开的一种方法包括去除牺牲栅极结构从而限定替代栅极腔，通过替代栅极腔执行蚀刻工艺，以在半导体材料层内限定使用暴露在内部的图案化硬掩模的鳍结构 替换栅极腔作为蚀刻掩模，并且在所述鳍状结构的至少一部分周围的所述替换栅极腔中形成替换栅极结构。

公开(公告)号：US20150137308A1

公开(公告)日：2015-05-21

申请号：US14083571

申请日：2013-11-19

Applicant: International Business Machines Corporation ,  Renesas Electronics Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

公开(公告)号：US20150129962A1

公开(公告)日：2015-05-14

申请号：US14078979

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/423

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/78603

Abstract: One method disclosed includes, among other things, removing a sacrificial gate structure to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to define a fin structure in a layer of semiconductor material using a patterned hard mask exposed within the replacement gate cavity as an etch mask and forming a replacement gate structure in the replacement gate cavity around at least a portion of the fin structure.

Abstract translation: 所公开的一种方法包括去除牺牲栅极结构从而限定替代栅极腔，通过替代栅极腔执行蚀刻工艺，以在半导体材料层内限定使用暴露在内部的图案化硬掩模的鳍结构 替换栅极腔作为蚀刻掩模，并且在所述鳍状结构的至少一部分周围的所述替换栅极腔中形成替换栅极结构。

公开(公告)号：US20150126008A1

公开(公告)日：2015-05-07

申请号：US14069868

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Abhijeet Paul ,  Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 所述方法包括在形成在衬底鳍上方的空腔中形成不同半导体材料的这种交替层，然后使用栅极第一或栅极末端技术在鳍周围形成栅极结构。

公开(公告)号：US20150123166A1

公开(公告)日：2015-05-07

申请号：US14069955

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Michael Hargrove ,  Ruilong Xie

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

Abstract: are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Abstract translation: 是涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 本文公开的方法和装置包括形成掺杂的硅衬底鳍片，然后在衬底鳍片周围形成硅/锗层。 所述方法和装置还包括使用栅极第一或栅极末端技术在硅/锗层周围形成栅极结构。

公开(公告)号：US08809947B1

公开(公告)日：2014-08-19

申请号：US13905741

申请日：2013-05-30

Applicant: GlobalFoundries, Inc.

Inventor： Kerem Murat Akarvardar ,  Ajey Poovannummoottil Jacob

IPC: H01L29/08 ,  H01L29/16 ,  H01L29/78 ,  H01L21/20

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate. The method etches the semiconductor substrate to form a non-planar transistor structure having sidewalls. On a standard (100) substrate the fin sidewalls have (110) surface plane if the fins are aligned or perpendicular with the wafer notch. The method includes depositing a sacrificial liner along the sidewalls of the non-planar transistor structure. Further, a confining material is deposited overlying the semiconductor substrate and adjacent the sacrificial liner. The method includes removing at least a portion of the sacrificial liner and forming a void between the sidewalls of the non-planar transistor structure and the confining material. A cladding layer is epitaxially grown in the void. Since the sidewall growth is limited by the confining material, a cladding layer of uniform thickness is enabled on fins with (110) sidewall and (100) top surface.

Abstract translation: 在示例性实施例中，制造集成电路的方法包括提供半导体衬底。 该方法蚀刻半导体衬底以形成具有侧壁的非平面晶体管结构。 在标准（100）<110>衬底上，如果翅片与<110>晶片切口对准或垂直，翅片侧壁具有（110）表面。 该方法包括沿非平面晶体管结构的侧壁沉积牺牲衬垫。 此外，将约束材料沉积在半导体衬底上并且邻近牺牲衬垫。 该方法包括去除牺牲衬垫的至少一部分并在非平面晶体管结构的侧壁与限制材料之间形成空隙。 在空隙中外延生长包层。 由于侧壁生长被限制材料限制，因此在具有（110）侧壁和（100）顶表面的翅片上能够实现均匀厚度的包覆层。