公开(公告)号：US09117930B2

公开(公告)日：2015-08-25

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。

公开(公告)号：US09362277B2

公开(公告)日：2016-06-07

申请号：US14175827

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L21/8238 ,  H01L21/205 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract translation: 公开了一种形成具有小占地面积的多值逻辑晶体管的方法和所得到的器件。 实施例包括在硅衬底上形成多个翅片，每个翅片用硬掩模覆盖; 用氧化物填充翅片和硬掩模之间的空间; 去除硬掩模并使每个翅片凹陷，在每个翅片上的氧化物中形成空腔; 在每个空腔中形成多个Si基层，其中Ge或C的百分比增加或掺杂剂浓度从底层到顶层的浓度降低; 执行CMP以平坦化到翅片的顶部; 将氧化物凹陷到具有等于每个Si基层的厚度的厚度的略微低于翅片顶部的深度; 以及在多个Si基层上形成高k栅极电介质和金属栅电极。

公开(公告)号：US20140346605A1

公开(公告)日：2014-11-27

申请号：US13902459

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Peter Zeitzoff ,  Abhijeet Paul

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, an integrated circuit includes a semiconductor substrate with a fin structure overlying the semiconductor substrate and having a source region, a drain region, and a channel region between the source region and drain region. The source region and the drain region each have a recessed surface. A source contact is adjacent the recessed surface in the source region and a drain contact is adjacent the recessed surface in the drain region. Linear current paths are defined from the channel region to the source contact and from the channel region to the drain contact.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 根据示例性实施例，集成电路包括半导体衬底，其半导体衬底具有覆盖在半导体衬底上的鳍状结构，并具有源极区域，漏极区域和源极区域与漏极区域之间的沟道区域。 源极区域和漏极区域各自具有凹入表面。 源极接触件邻近源极区域中的凹陷表面，并且漏极接触邻近漏极区域中的凹陷表面。 线路电流路径从通道区域到源极触点以及从沟道区域到漏极接触点定义。

公开(公告)号：US10756213B2

公开(公告)日：2020-08-25

申请号：US16433626

申请日：2019-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/10 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US10388790B2

公开(公告)日：2019-08-20

申请号：US15082103

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/10

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US20150126008A1

公开(公告)日：2015-05-07

申请号：US14069868

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Abhijeet Paul ,  Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 所述方法包括在形成在衬底鳍上方的空腔中形成不同半导体材料的这种交替层，然后使用栅极第一或栅极末端技术在鳍周围形成栅极结构。

公开(公告)号：US08889500B1

公开(公告)日：2014-11-18

申请号：US13960244

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

IPC: H01L21/338 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fin-formation trenches that define a fin, forming a first stressed layer within the trenches and above the fin and performing at least one etching process on the first stressed layer so as to define spaced-apart portions of the first stressed layer positioned at least partially within the trenches on opposite sides of the fin. The method also includes forming spaced-apart portions of a second stressed layer above the spaced-apart portions of the first layer, forming a third stressed layer above the fin between the spaced-apart portions of the second layer and, after forming the third layer, forming a conductive layer above the second and third layers.

Abstract translation: 本文公开的一种说明性方法包括形成限定翅片的多个翅片形成沟槽，在沟槽内和翅片上方形成第一应力层，并在第一应力层上执行至少一个蚀刻工艺，以便 以限定至少部分地位于鳍片的相对侧上的沟槽内的第一应力层的间隔开的部分。 该方法还包括在第一层的间隔开的部分上方形成第二应力层的间隔开的部分，在第二层间隔开的部分之间形成翅片之上的第三应力层，在形成第三层之后 在第二层和第三层上形成导电层。

公开(公告)号：US09219062B2

公开(公告)日：2015-12-22

申请号：US13902459

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Peter Zeitzoff ,  Abhijeet Paul

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In accordance with an exemplary embodiment, an integrated circuit includes a semiconductor substrate with a fin structure overlying the semiconductor substrate and having a source region, a drain region, and a channel region between the source region and drain region. The source region and the drain region each have a recessed surface. A source contact is adjacent the recessed surface in the source region and a drain contact is adjacent the recessed surface in the drain region. Linear current paths are defined from the channel region to the source contact and from the channel region to the drain contact.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 根据示例性实施例，集成电路包括半导体衬底，其半导体衬底具有覆盖在半导体衬底上的鳍状结构，并具有源极区域，漏极区域和源极区域与漏极区域之间的沟道区域。 源极区域和漏极区域各自具有凹入表面。 源极接触件邻近源极区域中的凹陷表面，并且漏极接触邻近漏极区域中的凹陷表面。 线路电流路径从通道区域到源极触点以及从沟道区域到漏极接触点定义。

公开(公告)号：US09023705B1

公开(公告)日：2015-05-05

申请号：US14069868

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Abhijeet Paul ,  Ajey Poovannummoottil Jacob ,  Min-hwa Chi

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8232 ,  H01L29/423 ,  H01L27/088 ,  H01L27/105 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/8232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/105 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 所述方法包括在形成在衬底鳍上方的空腔中形成不同半导体材料的这种交替层，然后使用栅极第一或栅极末端技术在鳍周围形成栅极结构。

公开(公告)号：US20150041906A1

公开(公告)日：2015-02-12

申请号：US13960200

申请日：2013-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, JR.

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。