公开(公告)号：US20080219054A1

公开(公告)日：2008-09-11

申请号：US12039461

申请日：2008-02-28

申请人： Fumitaka ARAI ,  Masaru Kito ,  Mitsuru Sato

发明人： Fumitaka ARAI ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration.

摘要翻译： 半导体存储器件包括多个有源区，每个有源区各自沿第一方向延伸，并且包括存储单元串，该存储单元串包括选择晶体管和存储单元，其电流通路串联连接，第一延伸部分设置在一侧 在与第一方向相反的第二方向上相邻的两个有效区域的末端部分和设置在与第二方向相邻的两个有效区域的另一侧终端部分之间的第二延伸部分，第一和第二延伸部分 以循环配置连接两个活动区域。

公开(公告)号：US07091546B2

公开(公告)日：2006-08-15

申请号：US11038173

申请日：2005-01-21

申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

IPC分类号： H01L29/772

CPC分类号： H01L27/10867

摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor formed so as to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，形成为沟槽电容器的单元晶体管，并且具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

公开(公告)号：US20080017992A1

公开(公告)日：2008-01-24

申请号：US11826224

申请日：2007-07-13

申请人： Masaru Kito ,  Mitsuru Sato ,  Yuzo Nagata ,  Koji Hashimoto

发明人： Masaru Kito ,  Mitsuru Sato ,  Yuzo Nagata ,  Koji Hashimoto

IPC分类号： H01L21/311 ,  H01L23/48

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L27/105 ,  H01L27/1052

摘要： A first hard mask is formed on a polysilicon film or a target member to be etched, on which a second hard mask composed of amorphous silicon is formed. Ions of boron or the like are implanted into a desired portion of the second hard mask, and then the first hard mask is etched with a mask of the second hard mask. Only the portion not ion-implanted of the second hard mask is etched off by wet etching. A sidewall film is formed on sidewalls of the first hard mask, and then the first hard mask having an upper portion exposed, not covered with the second hard mask is selectively etched off.

摘要翻译： 第一硬掩模形成在多晶硅膜或要蚀刻的靶构件上，在其上形成由非晶硅构成的第二硬掩模。 将硼等的离子注入到第二硬掩模的期望部分中，然后用第二硬掩模的掩模蚀刻第一硬掩模。 通过湿式蚀刻仅蚀刻第二硬掩模未离子注入的部分。 在第一硬掩模的侧壁上形成侧壁膜，然后选择性地蚀刻除去未被第二硬掩模覆盖的具有暴露的上部的第一硬掩模。

公开(公告)号：US07813203B2

公开(公告)日：2010-10-12

申请号：US12039461

申请日：2008-02-28

申请人： Fumitaka Arai ,  Masaru Kito ,  Mitsuru Sato

发明人： Fumitaka Arai ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： G11C7/02

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration.

摘要翻译： 半导体存储器件包括多个有源区，每个有源区各自沿第一方向延伸，并且包括存储单元串，该存储单元串包括选择晶体管和存储单元，其电流通路串联连接，第一延伸部分设置在一侧 在与第一方向相反的第二方向上相邻的两个有效区域的末端部分和设置在与第二方向相邻的两个有效区域的另一侧终端部分之间的第二延伸部分，第一和第二延伸部分 以循环配置连接两个活动区域。

公开(公告)号：US20050184323A1

公开(公告)日：2005-08-25

申请号：US11038173

申请日：2005-01-21

申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10

CPC分类号： H01L27/10867

摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor adjacently formed to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，与沟槽电容器相邻形成并具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域的单元晶体管， 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区域之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

公开(公告)号：US20140061773A1

公开(公告)日：2014-03-06

申请号：US13728311

申请日：2012-12-27

申请人： Masaaki HIGUCHI ,  Masaru Kito

发明人： Masaaki HIGUCHI ,  Masaru Kito

IPC分类号： H01L29/792

CPC分类号： H01L27/105 ,  H01L21/8229 ,  H01L21/8239 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11582 ,  H01L29/685 ,  H01L29/792

摘要： According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of insulative separating films, a channel body, and a memory film. The stacked body includes a plurality of electrode layers and a plurality of insulating layers. The plurality of insulative separating films separates the stacked body into a plurality. The channel body extends in the stacking direction between the plurality of insulative separating films. A width of the electrode layer of a lower layer side between the insulative separating film and the memory film is greater than a width of the electrode layer of an upper layer side between the insulative separating film and the memory film. An electrical resistivity of the electrode layer is higher for the electrode layer of the lower layer side having the greater width than for the electrode layer of the upper layer side having the lesser width.

摘要翻译： 根据一个实施例，半导体存储器件包括衬底，层叠体，多个绝缘分离膜，通道体和存储膜。 层叠体包括多个电极层和多个绝缘层。 多个绝缘分离膜将堆叠体分离成多个。 通道体在层叠方向上在多个绝缘分离膜之间延伸。 绝缘分离膜和记忆膜之间的下层侧的电极层的宽度大于绝缘分离膜和记忆膜之间的上层侧的电极层的宽度。 对于具有比具有较小宽度的上层侧的电极层的宽度大的下层侧的电极层，电极层的电阻率较高。

公开(公告)号：US20110051527A1

公开(公告)日：2011-03-03

申请号：US12725827

申请日：2010-03-17

申请人： Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

发明人： Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

IPC分类号： G11C16/04 ,  G11C16/02

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.

摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。 在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高 而不是V3到第二布线，或将第二布线置于浮置状态。

公开(公告)号：US20090184365A1

公开(公告)日：2009-07-23

申请号：US12352673

申请日：2009-01-13

申请人： Katsuyuki SEKINE ,  Masaru Kito ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Masaru Kito ,  Yoshio Ozawa

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L27/1203 ,  H01L29/40117 ,  H01L29/4234

摘要： A semiconductor memory device includes a tunnel insulating film, charge storage layer, block insulating film and control gate electrode stacked and formed on the surface of a semiconductor substrate. The charge storage layer is formed of an insulating film containing nitrogen. A dopant that reduces the trap density of charges moved in and out of an internal portion of the charge storage layer via the tunnel insulating film is doped into a region of the charge storage layer on the interface side with the tunnel insulating film or a dopant is doped into the above region with higher concentration in comparison with that of another region.

摘要翻译： 半导体存储器件包括层叠并形成在半导体衬底的表面上的隧道绝缘膜，电荷存储层，块绝缘膜和控制栅电极。 电荷存储层由含氮的绝缘膜形成。 通过隧道绝缘膜将电荷存储层的内部部分移入和移出的电荷的陷阱密度降低的掺杂剂掺杂到与隧道绝缘膜或掺杂剂的界面侧的电荷存储层的区域中 与其他区域相比，掺杂到上述区域中的浓度更高。

公开(公告)号：US07151290B2

公开(公告)日：2006-12-19

申请号：US10898358

申请日：2004-07-26

申请人： Masaru Kito

发明人： Masaru Kito

IPC分类号： H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/10861

摘要： A semiconductor device includes a conductive film that is filled in a trench formed in a semiconductor substrate via a first insulating film. The conductive film has a first portion and a second portion with an upper surface higher than the first portion. A second insulating film provided on the first portion of the conductive film has a first portion and a second portion whose upper surface is higher than the surface of the semiconductor substrate. The first portion of the second insulating film contacts the second portion of the second insulating film and has an upper surface lower than the surface of the second portion of the conductive film. A first gate electrode and a second gate electrode are provided on the second insulating film and above the semiconductor substrate, respectively. A connection conductive layer extends on the conductive film and on one of source/drain diffusion layers.

摘要翻译： 半导体器件包括通过第一绝缘膜填充在形成在半导体衬底中的沟槽中的导电膜。 导电膜具有第一部分和第二部分，其上表面高于第一部分。 设置在导电膜的第一部分上的第二绝缘膜具有第一部分和第二部分，其上表面高于半导体衬底的表面。 第二绝缘膜的第一部分接触第二绝缘膜的第二部分，并且具有比导电膜的第二部分的表面低的上表面。 分别在第二绝缘膜上和半导体衬底之上设置第一栅电极和第二栅电极。 连接导电层在导电膜上和源极/漏极扩散层之一上延伸。

公开(公告)号：US5414234A

公开(公告)日：1995-05-09

申请号：US148053

申请日：1993-11-05

申请人： Masaru Kito

发明人： Masaru Kito

IPC分类号： B23K9/20

CPC分类号： B23K9/201

摘要： A welding comprises placing the end of a stud supported by a welding gun on a welding portion of a workpiece, producing an arc discharge across the stud and the workpiece, melting the end of the stud and a portion of the workpiece and bringing the end of the stud so as to abut on the melted portion of the workpiece. A hollow cylindrical member 21 is prepared so that the material has a larger inside diameter than an end 20 of a stud 19 and is made of a magnetic permeable material is prepared. During the arc discharge, the cylindrical member 21 is placed so that the hollow portion is positioned on the side of the workpiece opposite to the stud and corresponding to the end of the stud.

摘要翻译： 焊接包括将由焊枪支撑的螺柱的端部放置在工件的焊接部分上，从而产生穿过螺柱和工件的电弧放电，熔化螺柱的端部和工件的一部分，并使 螺柱，以便抵靠在工件的熔化部分上。 制备中空的圆柱形构件21，使得该材料具有比螺柱19的端部20更大的内径，并且由导磁材料制成。 在电弧放电期间，圆柱形部件21被放置成使得中空部分位于工件的与螺柱相对的侧面并且对应于螺柱的端部。