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    EFFICIENT SOLID STATE DRIVE DATA COMPRESSION SCHEME AND LAYOUT
    191.
    发明申请
    EFFICIENT SOLID STATE DRIVE DATA COMPRESSION SCHEME AND LAYOUT 审中-公开
    有效的固态驱动数据压缩方案和布局

    公开(公告)号：US20160378352A1

    公开(公告)日：2016-12-29

    申请号：US14751450

    申请日：2015-06-26

    Applicant: Intel Corporation

    Inventor： Jawad B. Khan ,  Richard P. Mangold ,  Vinodh Gopal ,  Rowel S. Garcia ,  Knut S. Grimsrud

    IPC: G06F3/06

    CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/401 ,  G06F2212/7203 ,  G06F2212/7205

    Abstract: Methods and apparatus related to efficient Solid State Drive (SSD) data compression scheme and layout are described. In one embodiment, logic, coupled to non-volatile memory, receives data (e.g., from a host) and compresses the data to generate compressed data prior to storage of the compressed data in the non-volatile memory. The compressed data includes a compressed version of the data, size of the compressed data, common meta information, and final meta information. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了与高效固态硬盘（SSD）数据压缩方案和布局相关的方法和设备。 在一个实施例中，耦合到非易失性存储器的逻辑从存储压缩数据到非易失性存储器之前接收数据（例如来自主机）并压缩数据以生成压缩数据。 压缩数据包括数据的压缩版本，压缩数据的大小，公共元信息和最终元信息。 还公开并要求保护其他实施例。

    Generating Multiple Secure Hashes from a Single Data Buffer
    192.
    发明申请
    Generating Multiple Secure Hashes from a Single Data Buffer 审中-公开

    公开(公告)号：US20160352512A1

    公开(公告)日：2016-12-01

    申请号：US15231595

    申请日：2016-08-08

    Applicant: Intel Corporation

    Inventor： Sean M. Gulley ,  Vinodh Gopal ,  Wajdi K. Feghali ,  James D. Guilford ,  Gilbert M. Wolrich ,  Kirk S. Yap

    IPC: H04L9/06 ,  G06F21/72 ,  H04L9/32

    CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F21/72 ,  H04L9/3242 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/20

    Abstract: One embodiment provides an apparatus. The apparatus includes a single instruction multiple data (SIMD) hash module configured to apportion at least a first portion of a message of length L to a number (S) of segments, the message including a plurality of sequences of data elements, each sequence including S data elements, a respective data element in each sequence apportioned to a respective segment, each segment including a number N of blocks of data elements and to hash the S segments in parallel, resulting in S segment digests, the S hash digests based, at least in part, on an initial value and to store the S hash digests; a padding module configured to pad a remainder, the remainder corresponding to a second portion of the message, the second portion related to the length L of the message, the number of segments and a block size; and a non-SIMD hash module configured to hash the padded remainder, resulting in an additional hash digest and to store the additional hash digest.

    SMS4 acceleration hardware
    193.
    发明授权
    SMS4 acceleration hardware 有权
    SMS4加速硬件

    公开(公告)号：US09503256B2

    公开(公告)日：2016-11-22

    申请号：US14582707

    申请日：2014-12-24

    Applicant: Intel Corporation

    Inventor： Kirk Yap ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

    IPC: H04L9/00 ,  H04L9/08 ,  H04L9/14

    CPC classification number: H04L9/0822 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

    Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

    Abstract translation: 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮密钥扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

    Vector compare instructions for sliding window encoding
    196.
    发明授权
    Vector compare instructions for sliding window encoding 有权
    用于滑动窗口编码的向量比较指令

    公开(公告)号：US09489199B2

    公开(公告)日：2016-11-08

    申请号：US13730732

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich

    IPC: G06F9/30 ,  G06F7/02 ,  G06K9/62 ,  H03M7/30

    CPC classification number: G06F9/30021 ,  G06F7/02 ,  G06F9/30036 ,  G06F2207/025 ,  G06K9/6201 ,  H03M7/3086

    Abstract: A processor is described having an instruction execution pipeline having a functional unit to execute an instruction that compares vector elements against an input value. Each of the vector elements and the input value have a first respective section identifying a location within data and a second respective section having a byte sequence of the data. The functional unit has comparison circuitry to compare respective byte sequences of the input vector elements against the input value's byte sequence to identify a number of matching bytes for each comparison. The functional unit also has difference circuitry to determine respective distances between the input vector's elements' byte sequences and the input value's byte sequence within the data.

    Abstract translation: 描述了具有指令执行流水线的处理器，其具有功能单元，以执行将矢量元素与输入值进行比较的指令。 矢量元素和输入值中的每一个具有识别数据内的位置的第一相应部分和具有数据的字节序列的第二相应部分。 功能单元具有比较电路，用于将输入向量元素的各个字节序列与输入值的字节序列进行比较，以识别每个比较的匹配字节数。 功能单元还具有差分电路，以确定输入向量的元素的字节序列与数据内的输入值的字节序列之间的相应距离。

    Methods and apparatus to parallelize data decompression
    197.
    发明授权
    Methods and apparatus to parallelize data decompression 有权
    并行化数据解压缩的方法和装置

    公开(公告)号：US09484954B1

    公开(公告)日：2016-11-01

    申请号：US14850721

    申请日：2015-09-10

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Sudhir K. Satpathy ,  Sanu K. Mathew

    IPC: H03M7/40 ,  H03M9/00

    CPC classification number: H03M7/3086 ,  H03M7/40 ,  H03M7/4037 ,  H03M7/6005 ,  H03M7/6023

    Abstract: Methods and apparatus to parallelize data decompression are disclosed. A method selects the initial starting positions in a compressed data bitstream. A first one of the initial starting positions is adjusted to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream. The decoding includes traversing the bitstream from the training position as though first data located at the training position is a valid token. The first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position is output. The first decoded data is merged with second decoded data generated by decoding a second segment of the bitstream. The decoding of the second segment starting from a second position in the bitstream is performed in parallel with the decoding of the first segment. The second segment precedes the first segment in the bitstream.

    Abstract translation: 公开了并行化数据解压缩的方法和装置。 方法选择压缩数据比特流中的初始起始位置。 通过对比特流中训练位置开始的比特流进行解码来调整初始起始位置中的第一个以确定第一调整的起始位置。 解码包括从训练位置遍历比特流，就像位于训练位置的第一数据是有效的令牌一样。 输出从第一调整开始位置开始对比特流的第一段进行解码而生成的第一解码数据。 第一解码数据与通过对位流的第二段进行解码而生成的第二解码数据合并。 与第一段的解码并行地执行从比特流中的第二位置开始的第二段的解码。 第二段在比特流中的第一段之前。

    SMS4 acceleration processors, methods, systems, and instructions
    199.
    发明授权
    SMS4 acceleration processors, methods, systems, and instructions 有权
    SMS4加速处理器，方法，系统和说明

    公开(公告)号：US09361106B2

    公开(公告)日：2016-06-07

    申请号：US14142724

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

    IPC: G06F21/00 ,  G06F9/30 ,  G06F21/60 ,  G06F9/38

    CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3895 ,  G06F21/602 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

    Abstract: A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more source packed data operands. The one or more source packed data operands are to have four 32-bit results of four prior SMS4 rounds. The one or more source operands are also to have a 32-bit value. An execution unit is coupled with the decode unit and the plurality of the packed data registers. The execution unit, in response to the instruction, is to store a 32-bit result of a current SMS4 round in a destination storage location that is to be indicated by the instruction.

    Abstract translation: 一方面的处理器包括多个打包数据寄存器和用于解码指令的解码单元。 该指令是指示一个或多个源打包数据操作数。 一个或多个源打包数据操作数具有四个先前的SMS4回合的四个32位结果。 一个或多个源操作数也具有32位值。 执行单元与解码单元和多个打包数据寄存器耦合。 执行单元响应于该指令，将当前SMS4的32位结果存储在要由指令指示的目的地存储单元中。

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