公开(公告)号：US20220208640A1

公开(公告)日：2022-06-30

申请号：US17138541

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Daniel Lee Revier

IPC: H01L23/373 ,  H01L23/532 ,  H01L21/78 ,  H01L21/3205 ,  H01L21/683

Abstract: In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.

公开(公告)号：US11254775B2

公开(公告)日：2022-02-22

申请号：US16229971

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo

IPC: C08F292/00 ,  C08F8/42 ,  C08L33/12 ,  C08K3/08 ,  C08K7/00 ,  C08J5/24 ,  G03F1/78 ,  C08K3/04 ,  C08J5/00 ,  C08L25/06

Abstract: A composite material comprises a polymer matrix having microstructure filler materials that comprise a plurality of interconnected units wherein the units are formed of connected tubes. The tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, growing or depositing a material on the metal microlattice such as graphene, hexagonal boron nitride or other ceramic, and subsequently removing the metal microlattice.

公开(公告)号：US11237223B2

公开(公告)日：2022-02-01

申请号：US16521053

申请日：2019-07-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jo Bito ,  Benjamin Stassen Cook ,  Dok Won Lee ,  Keith Ryan Green ,  Ricky Alan Jackson ,  William David French

IPC: G01R33/00 ,  G01R33/07 ,  B32B15/04 ,  G01D5/14 ,  G01R15/20 ,  G01R33/06 ,  G01R21/08 ,  G01R33/02

Abstract: A structure includes a substrate which includes a surface. The structure also includes a horizontal-type Hall sensor positioned within the substrate and below the surface of the substrate. The structure further includes a patterned magnetic concentrator positioned above the surface of the substrate, and a protective overcoat layer positioned above the magnetic concentrator.

公开(公告)号：US20210302308A1

公开(公告)日：2021-09-30

申请号：US17120339

申请日：2020-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeronimo Segovia Fernandez ,  Bichoy Bahr ,  Hassan Omar Ali ,  Benjamin Stassen Cook

IPC: G01N21/3504 ,  G01N21/61 ,  G01N21/27 ,  G01J5/08 ,  B81B3/00

Abstract: A differential nondispersive infrared (NDIR) sensor incorporates an infrared (IR) chopper and multiple multi-bit digital registers to store and compare parameter ratio values, as may be digitally calibrated to corresponding temperature values, from chopper clock cycle portions in which a plasmonic MEMS detector is irradiated by the IR chopper with such values from chopper clock cycle portions in which the IR detector is not irradiated by the IR chopper. The plasmonic MEMS detector is referenced to a reference MEMS device via a parameter-ratio engine. The reference device can include a broadband IR reflector or can have a lower-absorption metasurface pattern giving it a lower quality factor than the plasmonic detector. The resultant enhancements to accuracy and precision of the NDIR sensor enable it to be used as a sub-parts-per-million gas concentration sensor or gas detector having laboratory, commercial, in-home, and battlefield applications.

公开(公告)号：US20210151551A1

公开(公告)日：2021-05-20

申请号：US17163766

申请日：2021-02-01

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier

IPC: H01L49/02 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66

Abstract: In described examples, a method for fabricating a semiconductor device and a three dimensional structure, and packaging them together, includes: fabricating the integrated circuit on a substrate, immersing the substrate in a liquid encapsulation material, and illuminating the liquid encapsulation material to polymerize the liquid encapsulation material. Immersing the semiconductor device is performed to cover a layer of a platform in the liquid encapsulation material. The platform is a lead frame, a packaging substrate, or the substrate. The illuminating step targets locations of the liquid encapsulation material covering the layer. Illuminated encapsulation material forms solid encapsulation material that is fixedly coupled to contiguous portions of the semiconductor device and of the solid encapsulation material. The immersing and illuminating steps are repeated until a three dimensional structure is formed. The integrated circuit and the three dimensional structure are encapsulated in a single package.

公开(公告)号：US20210151357A1

公开(公告)日：2021-05-20

申请号：US17140886

申请日：2021-01-04

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier

IPC: H01L23/29 ,  H03H9/02 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L23/34 ,  G10K11/162

Abstract: An encapsulated integrated circuit includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. Within the encapsulation material, a phononic bandgap structure is configured to have a phononic bandgap with a frequency range approximately equal to a range of frequencies of thermal phonons produced by the IC die when the IC die is operating.

公开(公告)号：US20210118762A1

公开(公告)日：2021-04-22

申请号：US17114219

申请日：2020-12-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L27/02 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

公开(公告)号：US20210091012A1

公开(公告)日：2021-03-25

申请号：US17115734

申请日：2020-12-08

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Steven Kummerl ,  Kurt Peter Wachtler

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/495

Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

公开(公告)号：US10957635B2

公开(公告)日：2021-03-23

申请号：US16359628

申请日：2019-03-20

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Sreenivasan Koduri ,  Benjamin Stassen Cook

IPC: H01L21/48 ,  H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  C25D7/12 ,  C25D3/38 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L23/544

Abstract: A packaged semiconductor device includes a metal substrate having a first and second through-hole aperture having an outer ring, and metal pads around the apertures on dielectric pads. A first and second semiconductor die have a back side metal (BSM) layer on its bottom side are mounted top side up on a top portion of the apertures. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the apertures to provide a die attachment for the first and the second semiconductor die that fills a bottom portion of the apertures. Leads contact the metal pads, wherein the leads include a distal portion that extends beyond the metal substrate. Bondwires are between the metal pads and bond pads on the first and second semiconductor die, and a mold compound provides encapsulation for the packaged semiconductor device.

公开(公告)号：US10923457B2

公开(公告)日：2021-02-16

申请号：US16231555

申请日：2018-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Bichoy Bahr ,  Baher Haroun

IPC: H01L25/065 ,  H01F38/14 ,  H03B5/08 ,  H01L21/673

Abstract: A multi-die module includes a first die with a first device and a second die with a second device. The multi-die module also includes a contactless coupler configured to convey signals between the first device and the second device. The multi-die module also includes a coupling loss reduction structure.