公开(公告)号：US11868778B2

公开(公告)日：2024-01-09

申请号：US16937189

申请日：2020-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ganesh Dasika ,  Sergey Blagodurov ,  Seyedmohammad Seyedzadehdelcheh

IPC: G06F9/34 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F9/342 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30167 ,  G06F13/1657

Abstract: Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.

公开(公告)号：US11868221B2

公开(公告)日：2024-01-09

申请号：US17490862

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Vanchinathan Venkataramani ,  Paul J. Moyer

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/30 ,  G06F11/07 ,  G06F11/34

CPC classification number: G06F11/263 ,  G06F11/076 ,  G06F11/3037 ,  G06F11/3409 ,  G06F11/3457

Abstract: Techniques for performing cache operations are provided. The techniques include tracking performance events for a plurality of test sets of a cache, detecting a replacement policy change trigger event associated with a test set of the plurality of test sets, and in response to the replacement policy change trigger event, operating non-test sets of the cache according to a replacement policy associated with the test set.

公开(公告)号：US20240005601A1

公开(公告)日：2024-01-04

申请号：US17853136

申请日：2022-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Kiia K. Kallio ,  Jan Achrenius

IPC: G06T17/10 ,  G06T15/00 ,  G06T1/20 ,  G06T7/13

CPC classification number: G06T17/10 ,  G06T15/005 ,  G06T1/20 ,  G06T7/13

Abstract: Concurrently with performing a visibility pass to generate visibility data for two or more bins of an image, a processing system determines whether a primitive to be rendered covers at least a predetermined threshold percentage of a tile of the image. In response to the primitive coving at least the predetermined threshold percentage of the tile, the processing system stores the depth data of the primitive in a depth buffer for pixel-based rendering. In response to the primitive not covering at least the predetermined threshold percentage of the tile, the processing system fuses the primitive with one or more preceding primitives sharing an edge with the primitive in the tile to generate a fused primitive. In response to the fused primitive being valid in the tile, the processing system passes the depth data of the fused primitive to the depth buffer.

公开(公告)号：US20240004821A1

公开(公告)日：2024-01-04

申请号：US17853812

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Tresidder ,  Benjamin Tsien

IPC: G06F13/40 ,  G06F1/26

CPC classification number: G06F13/4004 ,  G06F1/26 ,  G06F2213/40

Abstract: Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the physical layer.

公开(公告)号：US20240004725A1

公开(公告)日：2024-01-04

申请号：US17854650

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Shang Yang ,  Arash Moghimi

IPC: G06F9/50

CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5038

Abstract: Systems, apparatuses, and methods for managing power allocation in a computing system. A system management unit detects a condition indicating a change in power is indicated. Such a change may be detecting an indication that a power change is either required, possible, or requested. In response to detecting a reduction in power is indicated, the system management unit identifies currently executing tasks of the computing system and accesses sensitivity data to determine which of a number of computing units (or power domains) to select for power reduction. Based at least in part on the data, a unit is identified that is determined to have a relatively low sensitivity to power state changes under the current operating conditions. A relatively low sensitivity indicates that a change in power to the corresponding unit will not have as significant an impact on overall performance of the computing system than if another unit was selected. Power allocated for the selected unit is then decreased.

公开(公告)号：US20240004664A1

公开(公告)日：2024-01-04

申请号：US17855727

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sree Harsha Kosuru ,  Eric Dixon ,  Erik Swanson ,  Michael Estlick ,  Patrick Michael Lowry

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30123

Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240004583A1

公开(公告)日：2024-01-04

申请号：US17854953

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Aaron John Nygren ,  Michael John Litt

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673

Abstract: A random-access memory (RAM) includes a plurality of memory banks, a memory channel interface circuit, and a metadata processing circuit. The memory channel interface circuit couples to a memory channel adapted for coupling to a memory controller. The metadata processing circuit is connected to the memory channel interface circuit and receiving a poison bit sent over the memory channel associated with a write command and write data for the write command. The RAM, responsive to the poison bit indicating that the write data is poisoned, stores at least one of: the poison bit and a code indicating a value of the poison bit in a selected memory bank.

公开(公告)号：US20240004453A1

公开(公告)日：2024-01-04

申请号：US17854858

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashwini Chandrashekhara Holla ,  Alexander S. Duenas ,  Xinzhe Li ,  Indrani Paul ,  Karthik Rao

IPC: G06F1/324

CPC classification number: G06F1/324

Abstract: Methods and systems are disclosed for managing the power consumed by cores of a system on chip (SoC). Techniques disclosed include obtaining application information that is indicative of an application being executed on the cores, detecting a workload associated with the application, and limiting one or more operating frequencies of the cores responsive to the detection of the workload. Techniques disclosed also include profiling the detected workload and limiting the one or more operating frequencies of the cores based on the profiling.

公开(公告)号：US20240004444A1

公开(公告)日：2024-01-04

申请号：US17855054

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Karthik Rao ,  Indrani Paul ,  Dana Glenn Lewis ,  Brett Danier Anil Ramautarsingh ,  Jeffrey Ka-Chun Lui ,  Prasanthy Loganaathan ,  Jun Huang ,  Ho Hin Lau ,  Zhidong Xu

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.

公开(公告)号：US11862640B2

公开(公告)日：2024-01-02

申请号：US17489276

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L27/12 ,  H01L23/48 ,  H01L21/84 ,  H01L23/528

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5286

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. One or more of these cells use a dual polarity local interconnect power connection to receive a voltage reference level from a backside bus. For example, a power supply reference voltage level is received by a p-type device from a backside bus where the connection traverses both a p-type local interconnect layer and an n-type local interconnect layer.