公开(公告)号：US07733119B1

公开(公告)日：2010-06-08

申请号：US11478707

申请日：2006-06-30

Applicant: Gautham Devendra Kamath

Inventor： Gautham Devendra Kamath

IPC: H03K17/16

CPC classification number: F17C13/002 ,  F17C13/005 ,  H03K19/1733

Abstract: Programming circuitry 200 includes a terminal 202 for coupling to a resistor having a resistance representing a corresponding programming state. Current control circuitry 204/205 selectively passes at least one exponentially weighted current through terminal 202. Detection Circuitry 201 then determines the resistance of the resistor from the at least one exponentially weighted current to determine the programming state.

Abstract translation: 编程电路200包括用于耦合到具有表示相应编程状态的电阻的电阻器的端子202。 电流控制电路204/205选择性地将至少一个指数加权的电流通过端子202.检测电路201然后从至少一个指数加权电流确定电阻器的电阻以确定编程状态。

公开(公告)号：US07719246B2

公开(公告)日：2010-05-18

申请号：US11967269

申请日：2007-12-31

Applicant: John L. Melanson

Inventor： John L. Melanson

IPC: G05F1/40

CPC classification number: H02M1/4225 ,  H03M3/476 ,  Y02B70/126 ,  Y02P80/112

Abstract: A power control system includes a switching power converter and a power factor correction (PFC) and output voltage controller. The switching power converter utilizes a nonlinear energy transfer process to provide power to a load. The PFC and output voltage controller generates a control signal to control power factor correction and voltage regulation of the switching power converter. The PFC and output voltage controller includes a nonlinear delta-sigma modulator that models the nonlinear energy transfer process of the switching power converter. The nonlinear delta-sigma modulator generates an output signal used to determine the control signal. By using the nonlinear delta-sigma modulator in a control signal generation process, the PFC and output voltage controller generates a spectrally noise shaped control signal. In at least one embodiment, noise shaping of the control signal improves power factor correction and output voltage regulation relative to conventional systems.

Abstract translation: 功率控制系统包括开关功率转换器和功率因数校正（PFC）和输出电压控制器。 开关电源转换器利用非线性能量传递过程为负载提供电力。 PFC和输出电压控制器产生控制信号，以控制开关电源转换器的功率因数校正和电压调节。 PFC和输出电压控制器包括非线性Δ-Σ调制器，其对开关功率转换器的非线性能量传递过程进行建模。 非线性Δ-Σ调制器产生用于确定控制信号的输出信号。 通过在控制信号生成过程中使用非线性Δ-Σ调制器，PFC和输出电压控制器产生频谱噪声形状的控制信号。 在至少一个实施例中，控制信号的噪声整形提高了相对于常规系统的功率因数校正和输出电压调节。

公开(公告)号：US07711974B1

公开(公告)日：2010-05-04

申请号：US11540443

申请日：2006-09-29

Applicant: Zhong You ,  Jieren Bian

Inventor： Zhong You ,  Jieren Bian

IPC: G06F1/00 ,  H03M1/66

CPC classification number: G06F1/04

Abstract: An apparatus and a method for clock mode determination utilizing SCLK auto-detection and generation circuitry at a serial port which has a reduced number of pin-count by eliminating the need for inputting a master input clock signal MCLK and/or a serial input clock signal SCLK. The SCLK auto-detection and generation circuitry includes a SCLK detector circuit, a serial mode detector circuit, an internal SCLK generator circuit, a multiplexer, and an edge detector circuit. The SCLK detector circuit is used to detect whether an external serial clock signal is present and to generate a selection signal. The serial mode detector is used to detect whether an incoming data signal is in a non-TDM mode or a TDM mode and to generate a mode signal.

Abstract translation: 一种在串行端口使用SCLK自动检测和产生电路的时钟模式确定的装置和方法，该串行端口通过不需要输入主输入时钟信号MCLK和/或串行输入时钟信号而减少引脚数量 SCLK。 SCLK自动检测和生成电路包括一个SCLK检测器电路，一个串行模式检测器电路，一个内部SCLK发生器电路，一个多路复用器和一个边沿检测电路。 SCLK检测器电路用于检测外部串行时钟信号是否存在并产生选择信号。 串行模式检测器用于检测输入数据信号是处于非TDM模式还是TDM模式，并产生模式信号。

公开(公告)号：US07643573B2

公开(公告)日：2010-01-05

申请号：US11378009

申请日：2006-03-17

Applicant: Murari Kejariwal ,  John R. Coupe, II

Inventor： Murari Kejariwal ,  John R. Coupe, II

IPC: H04L25/03 ,  H04L27/08 ,  H04L7/00

CPC classification number: H03F3/45188 ,  H03F3/45475 ,  H03F2200/331 ,  H03F2203/45032 ,  H03F2203/45371 ,  H03F2203/45396 ,  H03F2203/45486 ,  H03F2203/45504 ,  H03F2203/45631 ,  H03F2203/45634 ,  H03F2203/45726 ,  H03G1/0029 ,  H03G1/0088 ,  H03M1/129

Abstract: A data acquisition system includes a programmable gain amplifier, an analog-to-digital converter, a filter, and control circuitry. The programmable gain amplifier is operatively connected to receive an analog input signal on its input and generates an amplified signal on its output in accordance with gain control signals. The analog-to-digital converter is operatively connected to receive the amplified signal from the amplifier and generates a digitized signal on its output. The filter is operatively connected to receive the digitized signal from the converter and generates a filtered digital signal on its output. The control circuitry is operatively connected to the amplifier and to the converter and is also responsive to the gain control signals for dynamically adjusting power between the amplifier and converter when the gain control signals are changed.

Abstract translation: 数据采集​​系统包括可编程增益放大器，模数转换器，滤波器和控制电路。 可编程增益放大器可操作地连接以在其输入上接收模拟输入信号，并根据增益控制信号在其输出上产生放大信号。 模数转换器可操作地连接以从放大器接收放大的信号，并在其输出端产生数字化信号。 滤波器可操作地连接以接收来自转换器的数字化信号，并在其输出端产生滤波后的数字信号。 控制电路可操作地连接到放大器和转换器，并且当增益控制信号改变时也响应于增益控制信号来动态调整放大器和转换器之间的功率。

公开(公告)号：US07639002B1

公开(公告)日：2009-12-29

申请号：US11410362

申请日：2006-04-25

Applicant: Murari Kejariwal ,  Prisad Ammisetti ,  Axel Thomsen ,  John Laurence Melanson

Inventor： Murari Kejariwal ,  Prisad Ammisetti ,  Axel Thomsen ,  John Laurence Melanson

IPC: G01R31/28

CPC classification number: G01R31/31707

Abstract: A method of testing an integrated circuit including a plurality of test nodes includes initiating a test mode and, during a first time interval of the test mode, stepping a level of a supply current of the integrated circuit to a calibration level. Parameters are observed at the plurality of test nodes to detect errors during a second time interval of the test mode and the level of the supply current selectively stepped in response to a number of errors detected. The level of the supply current is decoded to identify the detected errors.

Abstract translation: 一种测试包括多个测试节点的集成电路的方法包括启动测试模式，并且在测试模式的第一时间间隔期间，使集成电路的电源电平的级别达到校准水平。 在多个测试节点处观察参数以在测试模式的第二时间间隔期间检测错误，并且响应于检测到的错误的数量选择性地步进电源电平。 电源电流的电平被解码以识别检测到的错误。

公开(公告)号：US07626360B2

公开(公告)日：2009-12-01

申请号：US11609894

申请日：2006-12-12

Applicant: John L. Melanson

Inventor： John L. Melanson

IPC: H02J7/00 ,  H02J7/04

CPC classification number: H02J7/0031 ,  H03K17/063 ,  H03K17/687 ,  H03K2217/0018

Abstract: A charge-pump biased battery protection circuit provides improved efficiency, reduced power dissipation, and reduced complexity in battery powered circuits. A charge pump is utilized to bias the gate of a single pass transistor such that the voltage between the pass transistor gate and the drain/source terminals of the pass transistor have a magnitude greater than the battery voltage, reducing the voltage drop across the pass transistor. The charge pump may be controlled in conformity with a sensed current through the pass transistor, so that at times of lower current loads, power is conserved. The bulk (body) of the pass transistor can be controlled using a resistor coupling a battery terminal to the bulk and a single switch coupling the bulk to a charger/load connection terminal, permitting a single pass transistor to be used for charging and discharging.

Abstract translation: 电荷泵偏置的电池保护电路提高了电池供电电路的效率，降低了功耗，降低了复杂性。 电荷泵用于偏置单通晶体管的栅极，使得通过晶体管栅极与通过晶体管的漏极/源极端子之间的电压具有大于电池电压的幅度，从而减小了通过晶体管两端的电压降 。 电荷泵可以根据通过传感晶体管的感测电流来控制，使得在较低电流负载的时候，功率被保存。 可以使用将电池端子连接到本体的电阻器和将体积耦合到充电器/负载连接端子的单个开关来控制传输晶体管的体（体），从而允许单路晶体管用于充电和放电。

公开(公告)号：US07596681B2

公开(公告)日：2009-09-29

申请号：US11388846

申请日：2006-03-24

Applicant: Ronald D. Wiese ,  Nariankadu D. Hemkumar ,  Sanjay Pillay

Inventor： Ronald D. Wiese ,  Nariankadu D. Hemkumar ,  Sanjay Pillay

IPC: G06F9/40

CPC classification number: G06F9/30145 ,  G06F9/30163 ,  G06F9/322 ,  G06F9/4486

Abstract: A processor and processing method for reusing arbitrary sections of program code provides improved upgrade capability for systems with non-alterable read only memory (ROM) and a more flexible instruction set in general. A specific program instruction is provided in the processor instruction set for directing program execution to a particular start address, where the start address is specified in conjunction with the specific program instruction. An end address is also specified in conjunction with the specific program instruction and the processor re-directs control upon completion of code execution between the start and end address to either another specified address, or to a stored program counter value corresponding to the next instruction in sequence after the specific program instruction. A loop count may also be supplied for repeatedly executing the code between the start and end address until the count has expired.

Abstract translation: 用于重用程序代码任意部分的处理器和处理方法为具有不可更改的只读存储器（ROM）的系统和一般更灵活的指令集提供了改进的升级能力。 在处理器指令集中提供特定的程序指令，用于将程序执行指向特定的起始地址，其中结合特定程序指令指定起始地址。 还结合特定程序指令指定结束地址，并且处理器在完成在开始和结束地址之间的代码执行到另一个指定的地址之间重新引导控制，或者对应于对应于下一个指令的存储的程序计数器值 特定程序指令后的序列。 还可以提供循环计数以在开始和结束地址之间重复执行代码，直到计数结束为止。

公开(公告)号：US07589766B2

公开(公告)日：2009-09-15

申请号：US10659472

申请日：2003-09-10

Applicant: Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

Inventor： Nadi R. Itani ,  Caiyi Wang ,  David R. Welland

IPC: H04N5/235 ,  H04N5/238

CPC classification number: H04N5/2352 ,  H04N5/243

Abstract: A selectable threshold multimode gain control apparatus and method for a charge coupled device (CCD) or CMOS imaging system includes an automatic gain control (AGC) circuit which continuously controls gain in said CCD system to produce a mutually continuous combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC, as well as shutter timing for shutter gain.

Abstract translation: 一种用于电荷耦合器件（CCD）或CMOS成像系统的可选阈值多模增益控制装置和方法，包括一自动增益控制（AGC）电路，其连续地控制所述CCD系统中的增益以产生相互连续的组合目标增益电平。 一种用于成像器件的处理系统包括用于产生成像器信号的相机系统，用于从成像器接收数据的相关双样本（CDS）电路，可变增益放大器（VGA），模数转换器（ADC） 耦合到所述CDS电路，耦合到所述ADC的数字增益电路（DGC）以及耦合到所述DGC的用于控制CDS电路和DGC的自动增益控制（AGC）电路以及用于快门增益的快门定时。

公开(公告)号：US07557661B1

公开(公告)日：2009-07-07

申请号：US11618784

申请日：2006-12-30

Applicant: John L. Melanson ,  Gautham Devendra Kamath

Inventor： John L. Melanson ,  Gautham Devendra Kamath

IPC: H03B1/00 ,  H03L7/06 ,  H03D3/18

CPC classification number: H03L7/1976 ,  H03L7/07

Abstract: A direct digital synthesis (DDS) hybrid phase-lock loop for low-jitter synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level. A DDS circuit provides a clock output and has an input for receiving a rational number. The rational number represents a ratio between the frequency of the clock output and the frequency of another stable clock provided to the circuit. In one implementation, a phase output of the DDS circuit is compared to a phase determined from an incoming timing reference and in another implementation, the low-jitter clock output is utilized to generate a phase number via a counter that is clocked by the clock output and captured by the timing reference.

Abstract translation: 用于低抖动同步的直接数字综合（DDS）混合锁相环提供了一种用于从具有高抖动电平的定时参考产生低抖动时钟的机制。 DDS电路提供时钟输出，并具有用于接收有理数的输入。 有理数表示时钟输出的频率与提供给电路的另一个稳定时钟的频率之间的比率。 在一个实现中，将DDS电路的相位输出与从输入定时参考确定的相位进行比较，在另一实现中，低抖动时钟输出用于经由计时器产生相位数，计数器由时钟输出 并由定时参考捕获。

公开(公告)号：US07554399B1

公开(公告)日：2009-06-30

申请号：US11862324

申请日：2007-09-27

Applicant: Johann Gaboriau ,  Lingli Zhang

Inventor： Johann Gaboriau ,  Lingli Zhang

IPC: H03F3/217

CPC classification number: H03F1/52 ,  H03F1/305 ,  H03F3/217 ,  H03F2200/03 ,  H03F2200/351

Abstract: A protection circuit and method for protecting switching power amplifier circuits during reset provides protection against latch-up and other failures due to energy returned from an inductive load when the amplifier is reset. Upon receipt of a reset indication, rather than immediately disabling the switching power output stage, the switching power output stage is driven toward a fifty-percent duty cycle of operation for a time period so that energy stored in inductance of the load is reduced, preventing back-currents that would otherwise may cause latch-up of the output stage when the switching power output stage is disabled. After the time period has elapsed, the switching power output stage is disabled. Alternatively, the current through the inductive load is measured and the switching power stage is disabled after the magnitude of the current has fallen below a threshold.

Abstract translation: 在复位期间保护开关功率放大器电路的保护电路和方法提供了保护，以防止当放大器被复位时由于感性负载返回的能量而导致的闩锁和其他故障。 在接收到复位指示时，不是立即禁用开关功率输出级，所以开关功率输出级在一段时间内被驱动到操作的百分之五十的占空比，从而减少存储在负载的电感中的能量，从而防止 当开关功率输出级被禁止时，否则可能导致输出级闭锁的反向电流。 经过了一段时间后，开关电源输出级被禁止。 或者，测量通过电感负载的电流，并且在电流的大小已经降到阈值以下之前禁用开关功率级。