公开(公告)号：US20230061392A1

公开(公告)日：2023-03-02

申请号：US17897372

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

公开(公告)号：US11587930B2

公开(公告)日：2023-02-21

申请号：US17159534

申请日：2021-01-27

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

公开(公告)号：US11355354B1

公开(公告)日：2022-06-07

申请号：US17157313

申请日：2021-01-25

Applicant: Applied Materials, Inc.

Inventor： Zeqing Shen ,  Bo Qi ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: H01L21/00 ,  H01L21/48 ,  H01L21/02

Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the silicon-containing precursor, the oxygen-containing precursor, and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a silicon-and-oxygen-and-carbon-containing layer on the substrate.

公开(公告)号：US11211286B2

公开(公告)日：2021-12-28

申请号：US16277104

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Gaurav Thareja ,  Sankuei Lin ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Ajay Bhatnagar ,  Anchuan Wang

IPC: H01L21/764 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/417

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

公开(公告)号：US20210351183A1

公开(公告)日：2021-11-11

申请号：US17307366

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Nitin K. Ingle ,  Fredrick Fishburn

IPC: H01L27/108

Abstract: Memory devices and methods of manufacturing memory devices are provided. Described are devices and methods where 3D pitch multiplication decouples high aspect ratio etch width from cell width, creating small cell active area pitch to allow for small DRAM die size.

公开(公告)号：US11101136B2

公开(公告)日：2021-08-24

申请号：US16416865

申请日：2019-05-20

Applicant: Applied Materials, Inc.

Inventor： Dongqing Yang ,  Tien Fak Tan ,  Peter Hillman ,  Lala Zhu ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Christopher Snedigar ,  Ming Xia

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311

Abstract: Embodiments of the present technology may include a method of etching. The method may include mixing plasma effluents with a gas in a first section of a chamber to form a first mixture. The method may also include flowing the first mixture to a substrate in a second section of the chamber. The first section and the second section may include nickel plated material. The method may further include reacting the first mixture with the substrate to etch a first layer selectively over a second layer. In addition, the method may include forming a second mixture including products from reacting the first mixture with the substrate.

公开(公告)号：US10796922B2

公开(公告)日：2020-10-06

申请号：US16665834

申请日：2019-10-28

Applicant: Applied Materials, Inc.

Inventor： Soonam Park ,  Yufei Zhu ,  Edwin C. Suarez ,  Nitin K. Ingle ,  Dmitry Lubomirsky ,  Jiayin Huang

IPC: H01J37/32 ,  H01L21/3213 ,  G01J3/02 ,  C23C16/50 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/66 ,  C23C16/44 ,  C23C16/452 ,  C23C16/455 ,  C23C16/52 ,  G01J3/443

Abstract: In an embodiment, a plasma source includes a first electrode, configured for transfer of one or more plasma source gases through first perforations therein; an insulator, disposed in contact with the first electrode about a periphery of the first electrode; and a second electrode, disposed with a periphery of the second electrode against the insulator such that the first and second electrodes and the insulator define a plasma generation cavity. The second electrode is configured for movement of plasma products from the plasma generation cavity therethrough toward a process chamber. A power supply provides electrical power across the first and second electrodes to ignite a plasma with the one or more plasma source gases in the plasma generation cavity to produce the plasma products. One of the first electrode, the second electrode and the insulator includes a port that provides an optical signal from the plasma.

公开(公告)号：US10727080B2

公开(公告)日：2020-07-28

申请号：US15972434

申请日：2018-05-07

Applicant: Applied Materials, Inc.

Inventor： Xikun Wang ,  Naomi Yoshida ,  Soumendra N. Barman ,  Nitin K. Ingle

IPC: H01L21/321 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/67 ,  H01J37/32 ,  H01L21/311

Abstract: Methods are described herein for etching tantalum-containing films with various potential additives while still retaining other desirable patterned substrate portions. The methods include exposing a tantalum-containing film to a chlorine-containing precursor (e.g. Cl2) with a concurrent plasma. The plasma-excited chlorine-containing precursor selectively etches the tantalum-containing film and other industrially-desirable additives. Chlorine is then removed from the substrate processing region. A hydrogen-containing precursor (e.g. H2) is delivered to the substrate processing region (also with plasma excitation) to produce a relatively even and residue-free tantalum-containing surface. The methods presented remove tantalum while retaining materials elsewhere on the patterned substrate.

公开(公告)号：US20190326123A1

公开(公告)日：2019-10-24

申请号：US16435910

申请日：2019-06-10

Applicant: Applied Materials, Inc.

Inventor： Zihui Li ,  Rui Cheng ,  Anchuan Wang ,  Nitin K. Ingle ,  Abhijit Basu Mallick

IPC: H01L21/3065

Abstract: Exemplary methods for selectively removing silicon (e.g. polysilicon) from a patterned substrate may include flowing a fluorine-containing precursor into a substrate processing chamber to form plasma effluents. The plasma effluents may remove silicon (e.g. polysilicon, amorphous silicon or single crystal silicon) at significantly higher etch rates compared to exposed silicon oxide, silicon nitride or other dielectrics on the substrate. The methods rely on the temperature of the substrate in combination with some conductivity of the surface to catalyze the etch reaction rather than relying on a gas phase source of energy such as a plasma.

公开(公告)号：US20190252239A1

公开(公告)日：2019-08-15

申请号：US16277104

申请日：2019-02-15

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Gaurav Thareja ,  San Kuei Lin ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Ajay Bhatnagar

IPC: H01L21/764 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.