公开(公告)号：US20240113233A1

公开(公告)日：2024-04-04

申请号：US17958290

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Shengsi LIU ,  Shao Ming KOH ,  Tahir GHANI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/785

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for techniques for creating a wall within a forkFET transistor structure, where the wall is adjacent to a first stack of nanoribbons on a first side of the wall and a second stack of nanoribbons on a second side of the wall opposite the first side of the wall. In embodiments, the wall extends beyond the top of the first stack of nanoribbons and electrically isolates a first gate metal coupled with the first stack of nanoribbons and a second gate metal coupled with the second stack of nanoribbons from each other. Other embodiments may be described and/or claimed.

公开(公告)号：US20240113108A1

公开(公告)日：2024-04-04

申请号：US17958285

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Leonard P. GULER ,  Hongqian SUN ,  Shengsi LIU ,  Tahir GHANI ,  Baofu ZHU

IPC: H01L27/088 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a wall within a metal gate cut in a transistor layer of a semiconductor device, where the wall includes a volume of a gas such as air, nitrogen, or another inert gas. Other embodiments may be described and/or claimed.

公开(公告)号：US20240113025A1

公开(公告)日：2024-04-04

申请号：US17958283

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L23/5283 ,  H01L29/0673

Abstract: Embodiments disclosed herein include an integrated circuit structure. In an embodiment, the integrated circuit structure comprises an interlayer dielectric (ILD), and an opening in the ILD. In an embodiment, a first layer lines the opening, and a second layer lines the first layer. In an embodiment, the second layer comprises a semi-metal or transition metal dichalcogenide (TMD). The integrated circuit structure may further comprise a third layer over the second layer.

公开(公告)号：US20240105803A1

公开(公告)日：2024-03-28

申请号：US17953096

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Dan S. LAVRIC ,  Charles H. WALLACE ,  Tahir GHANI ,  Saurabh ACHARYA ,  Thomas O'BRIEN

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/7854 ,  H01L29/78696

Abstract: Integrated circuit structures having trench contact depopulation structures, and methods of fabricating integrated circuit structures having trench contact depopulation structures, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate stack is over the vertical stack of horizontal nanowires. A dielectric trench structure is adjacent to the gate stack. A dielectric sidewall spacer is between the gate stack and the dielectric trench structure. A dielectric gate cut plug is extending through the gate stack, the dielectric sidewall spacer, and the dielectric trench structure.

公开(公告)号：US20240105598A1

公开(公告)日：2024-03-28

申请号：US17954201

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53257

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines on a same level and along a same direction, a first one of the plurality of conductive lines having a first width and a first composition, and a second one of the plurality of conductive lines having a second width and a second composition. The second width greater than the first width, and the second composition is different than the first composition. The integrated circuit structure also includes an inter-layer dielectric (ILD) structure having portions between adjacent ones of the plurality of conductive lines.

公开(公告)号：US20240047566A1

公开(公告)日：2024-02-08

申请号：US18379548

申请日：2023-10-12

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA ,  Biswajeet GUHA

IPC: H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/775 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

公开(公告)号：US20240006416A1

公开(公告)日：2024-01-04

申请号：US17855598

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Wilfred GOMES ,  Rishabh MEHANDRU ,  Cory WEBER

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

公开(公告)号：US20240006412A1

公开(公告)日：2024-01-04

申请号：US17855608

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Anand S. MURTHY ,  Rishabh MEHANDRU ,  Cory WEBER ,  Sagar SUTHRAM ,  Pushkar RANADE ,  Wilfred GOMES

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.

公开(公告)号：US20230422485A1

公开(公告)日：2023-12-28

申请号：US17851967

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Rishabh MEHANDRU ,  Cory WEBER ,  Anand S. MURTHY

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/522 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/10841 ,  H01L29/0673 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/78696

Abstract: Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.

公开(公告)号：US20230420456A1

公开(公告)日：2023-12-28

申请号：US17850782

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Debaleena NANDI ,  Imola ZIGONEANU ,  Gilbert DEWEY ,  Anant H. JAHAGIRDAR ,  Harold W. KENNEL ,  Pratik PATEL ,  Anand S. MURTHY ,  Chi-Hing CHOI ,  Mauro J. KOBRINSKY ,  Tahir GHANI

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/161 ,  H01L29/167

CPC classification number: H01L27/0886 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/161 ,  H01L29/167

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.