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    Packet storage based on packet properties
    205.
    发明授权
    Packet storage based on packet properties 有权

    公开(公告)号：US11750534B2

    公开(公告)日：2023-09-05

    申请号：US17122215

    申请日：2020-12-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody

    IPC: H04L49/90 ,  H04L49/109 ,  H04L69/22 ,  H04L67/568

    CPC classification number: H04L49/9042 ,  H04L49/109 ,  H04L67/568 ,  H04L69/22

    Abstract: In some examples, a system on chip (SOC) comprises a network switch configured to receive a packet and to identify a flow identifier (ID) corresponding to a header of the packet. The SOC comprises a direct memory access (DMA) controller coupled to the network switch, where the DMA controller is configured to divide the packet into first and second fragments based on the flow ID and to assign a first hardware queue to the first fragment and a second hardware queue to the second fragment, and wherein the DMA controller is further configured to assign memory regions to the first and second fragments based on the first and second hardware queues. The SOC comprises a snoopy cache configured to store the first fragment to the snoopy cache or to memory based on a first cache allocation command, where the first cache allocation command is based on the memory region assigned to the first fragment, where the snoopy cache is further configured to store the second fragment to the snoopy cache or to memory based on a second cache allocation command, and where the second cache allocation command is based on the memory region assigned to the second fragment.

    PCIe peripheral sharing
    207.
    发明授权
    PCIe peripheral sharing 有权

    公开(公告)号：US11609866B2

    公开(公告)日：2023-03-21

    申请号：US17073925

    申请日：2020-10-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Jason A. T. Jones

    IPC: G06F13/16 ,  G06F13/42 ,  G06F12/10

    Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

    Redundant communications for multi-chip systems
    209.
    发明授权
    Redundant communications for multi-chip systems 有权

    公开(公告)号：US11550674B2

    公开(公告)日：2023-01-10

    申请号：US17463232

    申请日：2021-08-31

    Applicant: Texas Instruments Incorporated

    Inventor： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha

    IPC: G06F11/14

    Abstract: An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.

    Efficient and flexible color processor
    210.
    发明授权
    Efficient and flexible color processor 有权

    公开(公告)号：US11546562B2

    公开(公告)日：2023-01-03

    申请号：US17497560

    申请日：2021-10-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Narendra Mody ,  Shashank Dabral ,  Rajasekhar Allu ,  Niraj Nandan

    IPC: H04N1/60 ,  H04N9/04 ,  G06T1/20 ,  H04N9/67

    Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.

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