公开(公告)号：US20190212643A1

公开(公告)日：2019-07-11

申请号：US16305308

申请日：2017-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jinyin WAN

IPC: G03F1/36 ,  G06F17/50

Abstract: A method for correction of an optical proximity effect, comprising: parsing and dividing the periphery of a design pattern to obtain segments to process; for a segment having a corner comprising a segment side (101) and an adjacent side (102) forming a corner relation with the segment side, setting a target point according to the following principle: when the length of the adjacent side (102) is greater than a preset length, the target point is set at the location of the outer end point (104) of the segment side; when the length of the adjacent side (102) is less than or equal to the preset length, the target point is set between the vertex (103) of the corner and the outer end point (104) of the segment side, and the less the length of the adjacent side (102), the further the target point from the location of the outer end point (104); and adjusting, according to a simulation difference of the target point, the design pattern until it conforms to a design target.

公开(公告)号：US10349185B2

公开(公告)日：2019-07-09

申请号：US15573235

申请日：2016-05-05

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yonggang Hu

IPC: H04R19/04 ,  H04R1/08 ,  B81B3/00 ,  H04R7/06 ,  H04R7/18 ,  H04R19/00

Abstract: An MEMS microphone comprises a substrate (100), a support portion (200), a superimposed layer (600), an upper plate (300) and a lower plate (400). The substrate (100) is provided with an opening (120) penetrating the middle thereof; the lower plate (400) is arranged above and spanning the substrate (100); the support portion (200) is fixed on the lower plate (400); the upper plate (300) is attached on the support portion (200); an accommodation cavity (500) is formed from the support portion (200), the upper plate (300) and the lower plate (400); the superimposed layer (600) is attached on an central region of the upper plate (300) or the lower plate (400), and insulation is achieved between the upper plate (300) and a lower plate (400).

公开(公告)号：US10347730B2

公开(公告)日：2019-07-09

申请号：US16064550

申请日：2017-04-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng Bian

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/033

Abstract: A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (10), a trench on the surface of the substrate (10), an insulating spacer (20) on the substrate (10), a gate oxide layer (41) on the inner surface of the trench, and a polysilicon gate (40) on the gate oxide layer (41). The insulating spacer (20) abuts against the trench by means of a slope structure (21) of the insulating spacer; the polysilicon gate (40) extends onto the insulating spacer (20) along the slope structure (21) in the trench; the insulating spacer (20) comprises a polysilicon gate pull-up area (22) that is concave downwards with respect to other parts of the insulating spacer (20); the polysilicon gate (40) extending out of the trench is rested on the polysilicon gate pull-up area (22).

公开(公告)号：US20190198494A1

公开(公告)日：2019-06-27

申请号：US16329665

申请日：2017-08-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Guangyang WANG

IPC: H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0274 ,  H01L23/528 ,  H01L23/60 ,  H01L27/088 ,  H02H9/00

Abstract: A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.

公开(公告)号：US10249707B2

公开(公告)日：2019-04-02

申请号：US15564727

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A laterally diffused metal oxide semiconductor field-effect transistor, comprising a substrate (110), a source electrode (150), a drain electrode (140), a body region (160), and a well region on the substrate, the well region comprising: an insertion-type well (122) having P-type doping, being arranged below the drain electrode and being connected to the drain electrode; N wells (124), arranged on two sides of the insertion-type well; and P wells (126), arranged next to the N wells and being connected to the N wells; the source electrode and the body region are arranged in the P well.

公开(公告)号：US20190027564A1

公开(公告)日：2019-01-24

申请号：US16064522

申请日：2017-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng BIAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A trench gate lead-out structure comprises a substrate (10), a trench formed in the surface of the substrate (10) and a first dielectric layer (22) on the substrate (10), and also comprises a polysilicon gate (31) at the inner surface of the trench. The trench is partially filled by the polysilicon gate (31), so that a recess exists in the trench above the polysilicon gate (31). A second dielectric layer (41) is filled in the recess. The trench gate lead-out structure also comprises a metal plug (50). The metal plug (50) downwards penetrates through the first dielectric layer (22) and then is inserted between the second dielectric layer (41) and the polysilicon gate (31), and accordingly is connected to the polysilicon gate (31).

公开(公告)号：US20180375512A1

公开(公告)日：2018-12-27

申请号：US15731768

申请日：2015-09-17

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD

Inventor： Yun GAO

IPC: H03K17/22 ,  G06F1/24 ,  G05F3/24 ,  H03K17/687

CPC classification number: H03K17/223 ,  G05F3/24 ,  G06F1/24 ,  H03K17/22 ,  H03K17/687

Abstract: A power on reset circuit, comprising: a threshold level control circuit (120) configured to set threshold level values of power on reset and power off reset; a capacitor charge and discharge circuit (130) configured to output a power on reset signal according to the threshold level values set by the threshold level control circuit; and a current bias circuit (110) configured to provide a reference current not varying with a power supply to the threshold level control circuit (120) and the capacitor charge and discharge circuit (130), comprising: a first reference current output terminal connected to the threshold level control circuit (120); a second reference current output terminal connected to the capacitor charge and discharge circuit (130); and a third reference current output terminal connected to the capacitor charge and discharge circuit (130).

公开(公告)号：US20180374925A1

公开(公告)日：2018-12-27

申请号：US16064550

申请日：2017-04-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zheng BIAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/033 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/4236 ,  H01L21/0337 ,  H01L21/76897 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7825

Abstract: A trench gate structure and a manufacturing method therefor. The trench structure comprises a substrate (10), a trench on the surface of the substrate (10), an insulating spacer (20) on the substrate (10), a gate oxide layer (41) on the inner surface of the trench, and a polysilicon gate (40) on the gate oxide layer (41). The insulating spacer (20) abuts against the trench by means of a slope structure (21) of the insulating spacer; the polysilicon gate (40) extends onto the insulating spacer (20) along the slope structure (21) in the trench; the insulating spacer (20) comprises a polysilicon gate pull-up area (22) that is concave downwards with respect to other parts of the insulating spacer (20); the polysilicon gate (40) extending out of the trench is rested on the polysilicon gate pull-up area (22).

公开(公告)号：US20180358390A1

公开(公告)日：2018-12-13

申请号：US15766428

申请日：2016-08-24

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Xinxin LIU ,  Xiaodong HE

IPC: H01L27/13 ,  H01L23/64 ,  H01L49/02 ,  H01L27/12

CPC classification number: H01L27/13 ,  H01L23/64 ,  H01L23/642 ,  H01L27/12 ,  H01L27/1203 ,  H01L28/40

Abstract: A dielectric capacitor includes: a bottom silicon layer (102); a buried oxide layer (104) formed on a surface of the bottom silicon layer (102); a top silicon layer (106) formed on a surface of the buried oxide layer (104); an interlayer dielectric layer (108) formed on a surface of the top silicon layer (106); a lower plate (110), an insulation layer (112), and an upper plate (114) sequentially formed on the interlayer dielectric layer (108) and forming the main portion of the dielectric capacitor; a shallow trench isolation structure (116) formed on the top silicon layer (106) and configured to isolate an active region; and a deep trench isolation structure (118) formed below the lower plate (110) and passing through the top silicon layer (106) to be connected to the buried oxide layer (104).

公开(公告)号：US20180286976A1

公开(公告)日：2018-10-04

申请号：US15766082

申请日：2016-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun QI ,  Guipeng SUN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/063 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/78 ,  H01L29/7833

Abstract: A laterally diffused metal-oxide semiconductor field-effect transistor, comprising a substrate, a first conductivity type well region, a second conductivity type well region, a drain electrode in the first conductivity type well region, a source electrode and a body region in the second conductivity type well region, and a gate electrode arranged across surfaces of the first conductivity type well region and the second conductivity type well region, and also comprising a floating layer ring arranged on the top of the first conductivity type well region and located between the gate electrode and the drain electrode and a plurality of groove polysilicon electrodes running through the floating layer ring and stretching into the first conductivity type well region.