中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

226 records (took 0.079 seconds)

    Method of fabricating a dual-level stacked flash memory cell with a MOSFET storage transistor
    212.
    发明授权
    Method of fabricating a dual-level stacked flash memory cell with a MOSFET storage transistor 失效
    制造具有MOSFET存储晶体管的双电平堆叠闪存单元的方法

    公开(公告)号：US06958271B1

    公开(公告)日：2005-10-25

    申请号：US10634042

    申请日：2003-08-04

    Applicant: James Pan ,  Ning Cheng ,  Christy Mein Chu Woo

    Inventor： James Pan ,  Ning Cheng ,  Christy Mein Chu Woo

    IPC: G11C7/00 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792

    CPC classification number: H01L21/28273 ,  G11C16/0475 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7923

    Abstract: The present invention relates to methods of fabricating dual-level flash memory cells. A first active region and a second active region are formed in a substrate. A trench is formed in the substrate between the first active region and the second active region. A first insulator dielectric is formed on the substrate and within the trench forming a vertical structure. A first poly layer is formed on the first insulator dielectric. A second insulator dielectric is formed on at least a portion of the first poly layer. A second poly layer is formed on the second insulator dielectric.

    Abstract translation: 本发明涉及制造双层闪存单元的方法。 在衬底中形成第一有源区和第二有源区。 在第一有源区和第二有源区之间的衬底中形成沟槽。 第一绝缘体电介质形成在衬底上并且在沟槽内形成垂直结构。 在第一绝缘体电介质上形成第一多晶硅层。 在第一多晶硅层的至少一部分上形成第二绝缘体电介质。 在第二绝缘体电介质上形成第二多晶硅层。

    Dual-level stacked flash memory cell with a MOSFET storage transistor
    213.
    发明申请
    Dual-level stacked flash memory cell with a MOSFET storage transistor 有权
    具有MOSFET存储晶体管的双电平堆叠闪存单元

    公开(公告)号：US20050232051A1

    公开(公告)日：2005-10-20

    申请号：US11154070

    申请日：2005-06-16

    Applicant: James Pan ,  Ning Chen ,  Christy Woo

    Inventor： James Pan ,  Ning Chen ,  Christy Woo

    IPC: G11C7/00 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792

    CPC classification number: H01L21/28273 ,  G11C16/0475 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7923

    Abstract: The present invention is a dual-level flash memory cell design that stores 3 or more bits of information per transistor. The dual-level memory cell stores two lower bits in a first level and stores an upper bit in a second level. The lower bits are programmed, erased and read by alternate modes of operation wherein active regions operate as source and drain, and then drain and source. The upper bit is programmed and erased independent of the lower bits. However, reading of the upper bit depends upon read values of the lower bits. Additional levels are employed to store more than 3 bits of information.

    Abstract translation: 本发明是一种双电平闪存单元设计，其存储每个晶体管3个或更多位的信息。 双级存储器单元存储第一级中的两个较低位，并将高位存储在第二级。 低位通过可选的工作模式进行编程，擦除和读取，其中有源区域作为源极和漏极，然后漏极和源极工作。 高位被编程和擦除，独立于低位。 然而，读取较高位取决于较低位的读取值。 采用附加级别来存储超过3位的信息。

    Low-power multiple-channel fully depleted quantum well CMOSFETs
    216.
    发明申请
    Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
    低功耗多通道全耗尽量子阱CMOSFET

    公开(公告)号：US20050104140A1

    公开(公告)日：2005-05-19

    申请号：US10706948

    申请日：2003-11-14

    Applicant: James Pan ,  John Pellerin ,  Jon Cheek

    Inventor： James Pan ,  John Pellerin ,  Jon Cheek

    IPC: H01L29/786 ,  H01L31/062

    CPC classification number: H01L29/78696 ,  H01L29/78639

    Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

    Abstract translation: 多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。 多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。 多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

    Gate dielectric quality for replacement metal gate transistors
    219.
    发明授权
    Gate dielectric quality for replacement metal gate transistors 失效
    更换金属栅极晶体管的栅极介电质量得到改善

    公开(公告)号：US06830998B1

    公开(公告)日：2004-12-14

    申请号：US10462667

    申请日：2003-06-17

    Applicant: James Pan ,  Paul Besser ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jinsong Yin

    Inventor： James Pan ,  Paul Besser ,  Christy Mei-Chu Woo ,  Minh Van Ngo ,  Jinsong Yin

    IPC: H01L213205

    CPC classification number: H01L29/66606 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545

    Abstract: Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.

    Abstract translation: 在更换金属栅极处理期间由于等离子体损坏引起的栅极介质劣化被固化并且通过在去除多晶硅栅极之后处理栅极电介质来防止进一步的等离子体劣化。 实施例包括在金属沉积之前的金属沉积和CMP之后的低温真空退火，在氧气和氩气中的退火，在金属沉积之前的臭氧或形成气体，或者在金属沉积之前的硅烷或乙硅烷中的热浸渍。

    Methods for improved metal gate fabrication
    220.
    发明授权
    Methods for improved metal gate fabrication 失效
    改进金属栅极制造的方法

    公开(公告)号：US06773978B1

    公开(公告)日：2004-08-10

    申请号：US10229690

    申请日：2002-08-28

    Applicant: Paul Raymond Besser ,  Eric Paton ,  James Pan

    Inventor： Paul Raymond Besser ,  Eric Paton ,  James Pan

    IPC: H01L218242

    CPC classification number: H01L21/28052 ,  H01L21/28097 ,  H01L29/7833

    Abstract: Methods are disclosed for manufacturing semiconductor devices with silicide metal gates, wherein a single-step anneal is used to react a metal such as cobalt or nickel with substantially all of a polysilicon gate structure while source/drain regions are covered. A second phase conductive metal silicide is formed consuming substantially all of the polysilicon and providing a substantially uniform work function at the silicide/gate oxide interface.

    Abstract translation: 公开了用于制造具有硅化物金属栅极的半导体器件的方法，其中使用单步退火来使诸如钴或镍的金属与基本上所有的多晶硅栅极结构反应，同时覆盖源极/漏极区域。 形成第二相导电金属硅化物，其基本上消耗所有多晶硅，并在硅化物/栅极氧化物界面处提供基本均匀的功函数。

Patent Agency Ranking