公开(公告)号：US06823312B2

公开(公告)日：2004-11-23

申请号：US09764575

申请日：2001-01-18

Applicant: Parul A. Mittal ,  Pradeep Kumar Dubey

Inventor： Parul A. Mittal ,  Pradeep Kumar Dubey

IPC: G10L1500

CPC classification number: G10L21/06

Abstract: The present invention provides a method and system for providing improved understandability of received speech characterized in that it includes input interface adapted to capture received speech signals connected to a speech recognition means for identifying the contents of the received speech connected to one input of a data processor adapted to perform improvement in understandability, a user profile storage connected to another input of said data processor for providing user specific improvement data, and an output generator connected to the output of said data processor to produce personalized output based on an individual's needs. The instant invention also provides a configured computer program product for carrying out the above method.

Abstract translation: 本发明提供了一种用于提供接收语音的改进的可理解性的方法和系统，其特征在于它包括适于捕获连接到语音识别装置的接收到的语音信号的输入接口，用于识别连接到数据处理器的一个输入端的接收到的语音的内容 适于执行可理解性的改进，连接到所述数据处理器的另一输入端以提供用户特定改进数据的用户简档存储器，以及连接到所述数据处理器的输出端的输出发生器，以根据个人的需要产生个性化输出。 本发明还提供了一种用于执行上述方法的配置的计算机程序产品。

公开(公告)号：US06560742B1

公开(公告)日：2003-05-06

申请号：US09457950

申请日：1999-12-09

Applicant: Pradeep Kumar Dubey ,  Sanjay Mukund Joshi ,  Marc Adam Kaplan

Inventor： Pradeep Kumar Dubey ,  Sanjay Mukund Joshi ,  Marc Adam Kaplan

IPC: H03M1300

CPC classification number: H03M13/091

Abstract: The present invention involves a method for generating a partial Cyclic Redundancy Checking (CRC) value of a first interval of data in a digital data stream. The method includes the step of loading a precomputed CRC value corresponding to a one bit followed by a predetermined number of zeros. The predetermined number of zeros correspond to the number of digits of a polynomial minus one. The first interval of data is partitioned into a plurality of bits. The precomputed CRC value corresponding to the one bit followed by the predetermined number of zeros is enabled, for each of the plurality of bits having a value of one. The enabled, precomputed CRC values are combined to generate the partial CRC value of the first interval of data. Advantageously, multiple copies of the process may be executed in parallel to achieve a large speed-up.

Abstract translation: 本发明涉及一种用于产生数字数据流中第一数据间隔的部分循环冗余校验（CRC）值的方法。 该方法包括加载与一位相对应的预计算CRC值的步骤，后跟预定数量的零。 预定数量的零对应于多项式的位数减1。 数据的第一间隔被分割成多个位。 对于具有值为1的多个比特中的每一个，启用对应于后面是预定数目的零的一个比特的预计算CRC值。 组合启用的预计算CRC值以产生第一数据间隔的部分CRC值。 有利地，可以并行地执行该过程的多个副本以实现大的加速。

公开(公告)号：US06556281B1

公开(公告)日：2003-04-29

申请号：US09575998

申请日：2000-05-23

Applicant: Pradeep Kumar Govil ,  Jorge Ivaldi

Inventor： Pradeep Kumar Govil ,  Jorge Ivaldi

IPC: G03B2758

CPC classification number: G03F7/70216 ,  G03F7/707 ,  G03F7/70708 ,  G03F7/70783

Abstract: A flexible chuck for supporting a substrate during lithographic processing is described. This flexible chuck includes an electrode layer, a piezoelectric layer disposed on the electrode layer, and a substrate support layer disposed above the piezoelectric layer. By providing electrical signals to the piezoelectric layer through the electrode layer, the support layer can be flexed, thereby changing surface topography on a substrate disposed on the flexible chuck. The contact layer can include projections, each of the projections corresponding to a respective electrode within the electrode layer. Furthermore, the substrate support layer can be formed of a conductive material and thus serve as the ground layer. Alternatively, separate substrate support and ground layers can be provided. The flexible chuck in accordance with the instant invention can be a vacuum chuck. Also described is a method of monitoring topographic changes in a flexible chuck in accordance with the instant invention.

Abstract translation: 描述了在光刻处理期间用于支撑衬底的柔性卡盘。 该柔性卡盘包括电极层，设置在电极层上的压电层和设置在压电层上方的基板支撑层。 通过通过电极层向压电层提供电信号，支撑层可以弯曲，从而改变设置在柔性卡盘上的基板上的表面形貌。 接触层可以包括突起，每个突起对应于电极层内的相应电极。 此外，基板支撑层可以由导电材料形成，因此用作接地层。 或者，可以提供单独的衬底支撑和接地层。 根据本发明的柔性卡盘可以是真空卡盘。 还描述了根据本发明监测柔性卡盘中的地形变化的方法。

公开(公告)号：US06327651B1

公开(公告)日：2001-12-04

申请号：US09149466

申请日：1998-09-08

Applicant: Pradeep Kumar Dubey ,  Brett Olsson ,  Charles Philip Roth ,  Keith Everett Diefendorf ,  Ronald Ray Hochsprung ,  Hunter Ledbetter Scales, III

Inventor： Pradeep Kumar Dubey ,  Brett Olsson ,  Charles Philip Roth ,  Keith Everett Diefendorf ,  Ronald Ray Hochsprung ,  Hunter Ledbetter Scales, III

IPC: G06F1500

CPC classification number: G06F7/766 ,  G06F5/015

Abstract: A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.

Abstract translation: 在处理器的多媒体设施内实现交叉开关以执行矢量置换操作，其中源操作数的字节在目标输出中重新排序。 然后，交叉开关重新用于需要复用或移位操作的其他指令，特别是其中附加多路复用器的大小或桶形移位器的大小和延迟是显着的那些指令。 例如，可以通过交叉开关和一个附加的多路复用器层或小桶形移位器以一个周期的等待时间来执行宽移位操作。 因此，交叉开关设备被重新使用，现在共享交叉开关的指令的性能得到改善，并且减少处理器内的多媒体设备所需的总面积。

公开(公告)号：US06202130B1

公开(公告)日：2001-03-13

申请号：US09061975

申请日：1998-04-17

Applicant: Hunter Ledbetter Scales, III ,  Keith Everett Diefendorff ,  Brett Olsson ,  Pradeep Kumar Dubey ,  Ronald Ray Hochsprung ,  Bradford Byron Beavers ,  Bradley G. Burgess ,  Michael Dean Snyder ,  Cathy May ,  Edward John Silha

Inventor： Hunter Ledbetter Scales, III ,  Keith Everett Diefendorff ,  Brett Olsson ,  Pradeep Kumar Dubey ,  Ronald Ray Hochsprung ,  Bradford Byron Beavers ,  Bradley G. Burgess ,  Michael Dean Snyder ,  Cathy May ,  Edward John Silha

IPC: G06F1200

CPC classification number: G06F9/30047 ,  G06F9/30101 ,  G06F12/0862 ,  G06F2212/6028

Abstract: A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).

Abstract translation: 数据处理系统包括耦合到具有诸如L1数据高速缓存（16）的第一存储器的存储器系统的数据处理器（10），其布置在较低分层级的第二存储器（例如L2高速缓存）。 在处理这些数据元素之前，数据处理器（10）将向量的数据元素预取到第一存储器中。 如果请求的数据元素不存在于第一存储器中，则向第二存储器发出加载请求，并将存储器层级降低到最低限度，直到所请求的数据元素被最终检索并存储在第一存储器中。 数据处理器（10）通过考虑数据元素的长度和向量的步幅继续预取向量的后续数据元素。 在一个实施例中，数据处理器（10）响应于单个数据流接触负载（DST）指令（100）将矢量预取到第一存储器中。

公开(公告)号：US5942608A

公开(公告)日：1999-08-24

申请号：US829166

申请日：1997-03-31

Applicant: Pradeep Kumar ,  Kailash Chand Gupta

Inventor： Pradeep Kumar ,  Kailash Chand Gupta

IPC: C07H21/00

CPC classification number: C07H21/00

Abstract: A process for preparing oligoribo- or oligodeoxyribonucleotides comprising treating an alkanediol or alkanetriol of formula I ##STR1## wherein R.sup.1 =H--(CH.sub.2).sub.n --; andR.sup.2 =--CH.sub.2 OH or --(CH.sub.2).sub.n --Hn=1-4;with 4,4'-dimethoxytrityl chloride to generate a monosubstituted tritylated compound of formula II ##STR2## wherein R.sup.3 =H--(CH.sub.2).sub.p --; andR.sup.4 =-CH.sub.2 OH or --(CH.sub.2).sub.p --H;R.sup.5 is 4,4'-dimethoxytrityl and concommitantly R.sup.6 is hydrogen, orR.sup.5 is hydrogen and concommitantly R.sup.6 is 4,4'-dimethoxytrityl;p=1-4;and treating the compound of formula II with one equivalent of a homobifunctional alkanedioic acid halide, and contacting the resulting mixture with a polymer support bearing hydroxyl or aminoalkyl functionalities.

Abstract translation: 一种制备寡核苷酸或寡脱氧核糖核苷酸的方法，包括处理式I的链烷二醇或烷三醇，其中R1 = H-（CH2）n-; R2 = -CH2OH或 - （CH2）n-Hn = 1-4; 与4,4'-二甲氧基三苯甲基氯反应以产生式II的单取代三苯甲基化合物，其中R 3 = H-（CH 2）p - ; 和R4 = -CH2OH或 - （CH2）p-H; R5是4,4'-二甲氧基三苯甲基，同时R6是氢，或R5是氢，并且R6是4,4'-二甲氧基三苯甲基; p = 1-4; 并用一当量的同双功能链烷二酰卤处理式II化合物，并将所得混合物与带有羟基或氨基烷基官能团的聚合物载体接触。

公开(公告)号：US5812811A

公开(公告)日：1998-09-22

申请号：US383331

申请日：1995-02-03

Applicant: Pradeep Kumar Dubey ,  Charles Marshall Barton ,  Chiao-Mei Chuang ,  Linh Hue Lam ,  John Kevin O'Brien ,  Kathryn Mary O'Brien

Inventor： Pradeep Kumar Dubey ,  Charles Marshall Barton ,  Chiao-Mei Chuang ,  Linh Hue Lam ,  John Kevin O'Brien ,  Kathryn Mary O'Brien

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3009 ,  G06F9/3842 ,  G06F9/3851

Abstract: A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future threads for parallel execution. The CPU has an instruction cache with one or more instruction cache ports, a bank of one or more program counters, a bank of one or more dispatchers, a thread management unit that handles inter-thread communications and discards future threads that violate dependencies, a set of architectural registers common to all threads, and a scheduler that schedules parallel execution of the instructions on one or more functional units in the CPU.

Abstract translation: 计算机中的中央处理单元（CPU），允许多个指令线程的推测并行执行。 CPU使用被添加到CPU的指令集中的Fork-Suspend指令，并在运行时插入到程序中，以描绘未来可能的并行线程。 CPU具有指令高速缓存，其具有一个或多个指令高速缓存端口，一个或多个程序计数器的存储体，一个或多个调度器的存储体，处理线程间通信的线程管理单元，并丢弃违反相关性的未来线程， 所有线程通用的一组架构寄存器，以及一个在CPU中的一个或多个功能单元上并行执行指令的调度程序。

公开(公告)号：US5774685A

公开(公告)日：1998-06-30

申请号：US426502

申请日：1995-04-21

Applicant: Pradeep Kumar Dubey

Inventor： Pradeep Kumar Dubey

IPC: G06F9/38 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F9/383 ,  G06F9/30047 ,  G06F12/127

Abstract: The computer processing unit of the present invention includes a new prefetch instruction, referred to as an STOUCH instruction, which provides the capability to encode compile-time speculations associated with the conditional branches between the time the prefetch request is initiated and the time the prefetched data is actually needed. As a result of this explicit communication of compile-time speculations to the run-time hardware, prefetched lines based on invalid speculations can be discarded earlier, whereas, prefetched lines based on valid speculations can be retained longer in the cache, leading to better cache performance.

Abstract translation: 本发明的计算机处理单元包括一个称为STOUCH指令的新的预取指令，该预取指令提供了在启动预取请求的时间与预取数据的时间之间编码与条件分支相关联的编译时间推测的能力 实际上是需要的 由于将编译时推测显式通信到运行时硬件，基于无效推测的预取行可以较早地被丢弃，而基于有效猜测的预取行可以在缓存中保留更长时间，从而导致更好的缓存 性能。

公开(公告)号：US5764155A

公开(公告)日：1998-06-09

申请号：US627342

申请日：1996-04-03

Applicant: Veronica Kertesz ,  Don Whitehead ,  James Burke ,  Harshad Tanna ,  Subhash Garg ,  A. Rajeshwar Rao ,  S. S. Lakshmi ,  S. Mishra ,  J. Lakshminarayana ,  Pradeep Kumar Tamanna ,  B. Ravi Kumar ,  M. Kailashnath

Inventor： Veronica Kertesz ,  Don Whitehead ,  James Burke ,  Harshad Tanna ,  Subhash Garg ,  A. Rajeshwar Rao ,  S. S. Lakshmi ,  S. Mishra ,  J. Lakshminarayana ,  Pradeep Kumar Tamanna ,  B. Ravi Kumar ,  M. Kailashnath

IPC: H02J13/00 ,  G06F13/00 ,  H04M11/00

CPC classification number: H02J13/0086

Abstract: A dynamic data exchange (DDE) server which allows external programs to access power management data is presented. The DDE server provides a mnemonic cross reference between register items and standardized, alphanumeric parameter names. This mnemonic interface allows the user to retrieve data from a device without knowledge of the actual device register item number. Also, the DDE server automatically performs time synchronizing for all supported devices and provides a consistent waveform and event interface. The DDE server is optimized for either the Modbus RTU or Ethernet protocol. The DDE server includes toolkit functions which are used to maintain DDE communication and protocol timers and to maintain active topic and item lists. The DDE server acts as a link between a client requesting device data and a field device which can provide the data. The DDE server communicates to the field device through communication ports and to the client via DDE message link. A client sends its requests to server to read/write some device registers. The server maps each request to suitable device read/write request packets and carries out the necessary transaction with device. Then it relays the result back to the client after processing and casting the collected device data to proper format.

Abstract translation: 介绍了允许外部程序访问电源管理数据的动态数据交换（DDE）服务器。 DDE服务器在注册表项和标准化的字母数字参数名称之间提供助记符交叉引用。 该助记符接口允许用户从设备中检索数据，而不了解实际的设备寄存器项目号码。 此外，DDE服务器会自动为所有受支持的设备执行时间同步，并提供一致的波形和事件接口。 DDE服务器针对Modbus RTU或以太网协议进行了优化。 DDE服务器包括用于维护DDE通信和协议定时器以及维护活动主题和项目列表的工具包功能。 DDE服务器充当客户端请求设备数据和可以提供数据的现场设备之间的链接。 DDE服务器通过通信端口和现场设备通过DDE消息链路与客户端进行通信。 客户端将其请求发送到服务器以读/写一些设备寄存器。 服务器将每个请求映射到适当的设备读/写请求数据包，并与设备执行必要的事务。 然后，在将收集的设备数据处理并转换为适当的格式后，将结果中继到客户端。

公开(公告)号：US5676256A

公开(公告)日：1997-10-14

申请号：US736275

申请日：1996-10-24

Applicant: Pradeep Kumar ,  Richard B. Wolanski ,  Mark S. Wolanski

Inventor： Pradeep Kumar ,  Richard B. Wolanski ,  Mark S. Wolanski

IPC: B07C5/342 ,  G06K9/46

CPC classification number: B07C5/3422 ,  B07C5/368 ,  G06K9/46 ,  Y10S209/938 ,  Y10S209/939

Abstract: A scrap particle sorting system and attendant sorting process employs a conveyor for conveying the randomly shaped particles in a random orientation, a position sensor for determining the advancement of the scrap particles in the direction of conveyance by determining the position of the conveyor belt, an image detector for periodically recording the image of a predefined viewing area through which the scrap particles are conveyed, and an image processor for periodic acquisition and processing of the images. The image processor includes logic for defining each image of the viewing area into a matrix of cells, and for each acquired image, analyzing the digital data corresponding to the image to determine for each cell in the matrix whether the pixels in that cell satisfy a predetermined criteria, and establishing a discriminator signal for each cell in the matrix as a function of that analysis. The system employs an image detector controller for receiving a signal from the conveyor position sensor and sending an activation signal to the image processor at timed intervals to acquire sequential image frames which include each of the scrap particles as they are conveyed past the viewing area, and a separator controller for receiving the discriminator signals from the image processor and for sending a control signal to selectively activate the appropriate portion of the separator to eject desired from undesired particles.

Abstract translation: 废料粒子分选系统和伴随分拣过程采用用于以随机取向输送随机形状的颗粒的输送机，用于通过确定输送带的位置来确定废料颗粒在输送方向上的前进的位置传感器，图像 用于周期性地记录传送废料颗粒的预定义观察区域的图像的检测器，以及用于周期性地获取和处理图像的图像处理器。 图像处理器包括用于将观看区域的每个图像定义成单元矩阵的逻辑，并且对于每个获取的图像，分析与图像相对应的数字数据，以确定矩阵中的每个单元是否满足预定的像素 标准，并且作为该分析的函数为矩阵中的每个单元建立鉴别器信号。 该系统采用图像检测器控制器，用于接收来自输送机位置传感器的信号，并以定时的间隔向图像处理器发送激活信号，以获取包括每个废料颗粒在传送通过观察区域时的每个废料颗粒的顺序图像帧;以及 分离器控制器，用于从图像处理器接收鉴别器信号，并发送控制信号以选择性地激活分离器的适当部分以从不期望的颗粒喷射所需的物体。