公开(公告)号：US20020016890A1

公开(公告)日：2002-02-07

申请号：US09885450

申请日：2001-06-20

Applicant: STMicroelectronics S.A.

Inventor： Sylvie Wuidart

IPC: G06F012/14

CPC classification number: G06F12/1441 ,  G06F12/1483

Abstract: A secured microprocessor includes a rights allocation system for the allocation, to programs executable by the microprocessor, of permanent access rights to certain zones of the memory array of the microprocessor. The rights allocation system confers, on a sub-program shared by at least two programs, temporary rights of access to certain memory zones. The temporary rights are allocated when the sub-program is called by one of the programs as a function of the program calling the sub-program. The rights allocation system provides libraries in a secured microprocessor without harming the integrity of the rights conferred on programs using the libraries.

Abstract translation: 安全微处理器包括用于分配的权限分配系统，可由微处理器执行的程序，对微处理器的存储器阵列的特定区域的永久访问权限。 权利分配制度赋予由至少两个方案共享的子方案获得某些内存区域的临时访问权限。 当子程序被其中一个程序调用作为调用子程序的程序的函数时，临时权限被分配。 权利分配系统在安全的微处理器中提供库，而不会损害使用库的程序授予的权利的完整性。

公开(公告)号：US20020015346A1

公开(公告)日：2002-02-07

申请号：US09879799

申请日：2001-06-12

Applicant: STMicroelectronics S.A.

Inventor： Francois Jacquet ,  Olivier Godcheau

IPC: G11C007/14

CPC classification number: G11C7/14 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4099

Abstract: A method is for controlling reading of a dynamic random access memory (DRAM) including memory cells connected to a bit line of a memory plane of the DRAM and associated with a main reference cell connected to a reference bit line. The method may include reading and refreshing the contents of the memory cell and pre-charging the bit line, the reference bit line and the main reference cell for a subsequent read access. During reading and refreshing the memory cell, the main reference cell and a secondary reference cell connected to the bit line may be activated and, after having deactivated the two reference cells, they are pre-charged to a final pre-charge voltage. The final pre-charge voltage may be chosen to be less than or greater than (as a function of the NMOS or PMOS technology used, respectively) half the sum of a high-state storage voltage and a low-state storage voltage.

Abstract translation: 一种用于控制动态随机存取存储器（DRAM）的读取的方法，所述动态随机存取存储器（DRAM）包括连接到DRAM的存储器平面的位线并与连接到参考位线的主参考单元相关联的存储器单元。 该方法可以包括读取和刷新存储器单元的内容并对位线预先充电，参考位线和主参考单元用于随后的读取访问。 在读取和刷新存储器单元期间，主参考单元和连接到位线的次参考单元可以被激活，并且在使两个参考单元停用之后，它们被预充电到最终的预充电电压。 最终的预充电电压可以被选择为小于或大于（作为分别使用的NMOS或PMOS技术的函数）作为高状态存储电压和低状态存储电压之和的一半。

公开(公告)号：US20010038341A1

公开(公告)日：2001-11-08

申请号：US09837629

申请日：2001-04-18

Applicant: STMicroelectronics S.A.

Inventor： Ahmed Kari ,  Michel Bardouillet

IPC: G08C019/00

CPC classification number: G06K19/07 ,  G01R31/007 ,  G01R31/026

Abstract: The circuit for detecting the frequency of binary signals includes a circuit for detecting rising edges in the binary signals, a measuring circuit for measuring the period between the rising edges which supplies a logic state, and a shift register whose input latch stores the logic state. Also, the detecting circuit includes a shift circuit for shifting logic states of the shift register, and a decoding circuit for decoding logic states of the register, and which supplies a signal validating the signals. The detecting circuit can be used in contactless chip card readers.

Abstract translation: 用于检测二进制信号的频率的电路包括用于检测二进制信号中的上升沿的电路，用于测量提供逻辑状态的上升沿之间的周期的测量电路和输入锁存器存储逻辑状态的移位寄存器。 此外，检测电路包括用于移位移位寄存器的逻辑状态的移位电路和用于解码寄存器的逻辑状态的解码电路，并提供验证信号的信号。 检测电路可用于非接触式芯片读卡器。

公开(公告)号：US20010030530A1

公开(公告)日：2001-10-18

申请号：US09826299

申请日：2001-04-04

Applicant: STMicroelectronics S.A.

Inventor： Nicolas Marty

IPC: G05F001/40

CPC classification number: G05F1/565 ,  G05F1/575

Abstract: A voltage regulator includes a regulation MOS transistor and an amplifier providing an output for driving a gate of the regulation MOS transistor. The amplifier drives the gate based upon a difference between a reference voltage and a feedback voltage. The voltage regulator may further include a circuit for making the amplifier switch to a standby mode with low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while maintaining, at the gate of the regulation transistor, a voltage that keeps the regulation transistor on. The present invention is particularly applicable to the management of power supplies in portable telephones.

Abstract translation: 电压调节器包括调节MOS晶体管和提供用于驱动调节MOS晶体管的栅极的输出的放大器。 放大器基于参考电压和反馈电压之间的差异驱动门。 电压调节器还可以包括用于当电源电压和调节器的输出电压之间的差低于第一阈值时使放大器开关进入具有低电流消耗的待机模式的电路。 这是在保持调节晶体管的栅极处保持调节晶体管导通的电压的同时完成的。 本发明特别适用于便携式电话中的电源的管理。

公开(公告)号：US20010028260A1

公开(公告)日：2001-10-11

申请号：US09795055

申请日：2001-02-26

Applicant: STMicroelectronics S.A.

Inventor： Christophe Garnier

IPC: H03K005/22

CPC classification number: H03K5/2481

Abstract: The device for the comparison of the levels of two input signals MI, PI includes a first comparator COMP1, the switching of the comparator being expressed by a change-over of the output OUT1 of the comparator from a first logic state into a second logic state, the change-over of the output OUT1 from one logic state null0null into the other state null1null being faster than the change-over in the other direction. The device also includes a second comparator COMP2 with an identical structure, to whose input the signals to be compared are applied invertedly so that the switching operations in the comparators are inverted. The output of each comparator is applied to an associated logic circuit 1, 2 capable of accelerating the inverse switching in the other comparator for a change in the output corresponding to the fastest change-over.

Abstract translation: 用于比较两个输入信号MI，PI的电平的装置包括第一比较器COMP1，比较器的切换由比较器的输出端OUT1从第一逻辑状态转换成第二逻辑状态 输出OUT1从一个逻辑状态“0”转换到另一状态“1”的转换比另一方向的转换快。 该装置还包括具有相同结构的第二比较器COMP2，与其输入相反的信号被反相地施加以使比较器中的开关操作反转。 每个比较器的输出被施加到相关联的逻辑电路1,2，其能够加速另一比较器中的反向切换，以对应于最快转换的输出变化。

公开(公告)号：US20010020857A1

公开(公告)日：2001-09-13

申请号：US09771364

申请日：2001-01-26

Applicant: STMicroelectronics S.A.

Inventor： Alexandre Malherbe ,  Fabrice Marinet ,  Alain Pomet

IPC: H03K005/01

CPC classification number: G06K19/07 ,  G06F13/426

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract translation: 用于从外部串行总线再生时钟信号的装置包括环形振荡器和计数器。 环形振荡器提供时钟信号的n个相位。 在这n个阶段中，使用一个相作为参考，并将其应用于计数器。 因此，可以对从总线接收的第一脉冲和第二脉冲之间的整个参考时钟信号周期的数量进行计数。 在接收到第二脉冲时读取振荡器中的相位状态，确定与基准时钟信号和总线的第二脉冲之间的相位延迟相对应的电流相位。 通过使用还包括环形振荡器和计数器的再生装置，可以高精度地重新生成总线的时钟信号。

公开(公告)号：US20010005618A1

公开(公告)日：2001-06-28

申请号：US09738870

申请日：2000-12-15

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Malgorzata Jurczak ,  Didier Dutartre

IPC: H01L021/00 ,  H01L021/84 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/76262 ,  H01L29/0673 ,  H01L29/0676

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

Abstract translation: 用于在隔离衬底上制造由单晶硅制成的纳米线网络的工艺包括制备包含限定主体中心部分的侧向隔离的硅体的衬底。 在具有由电介质材料制成的底壁的中心部分形成凹部，由电介质材料制成的第一对相对的平行侧壁和第二对相对的平行侧壁。 第二对的相对的平行侧壁中的至少一个由单晶硅形成。 该方法还包括从由凹槽的单晶硅制成的侧壁，由单晶SiGe合金和单晶硅制成的平行线的交替网络的凹槽中的外延生长。 此外，由单晶SiGe合金制成的线被蚀刻以在凹槽中形成由彼此绝缘的单晶硅硅制成的平行线的网络。

公开(公告)号：US10680630B1

公开(公告)日：2020-06-09

申请号：US16439038

申请日：2019-06-12

Applicant: STMicroelectronics S.A.

Inventor： Olivier David

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/08

Abstract: An interleaved analog to digital converter (“ADC”) includes a first ADC having an input for sampling an analog signal during a first time period, an output for providing a digital signal, and a power supply terminal for receiving a first power supply voltage, a second ADC having an input for sampling the analog signal during a second time period, an output for providing a digital signal, and a power supply terminal for receiving a second power supply voltage, a first skew estimator for estimating a skew value of the first ADC, a second skew estimator for estimating a skew value of the second ADC, and a comparator for comparing the skew values, adjusting the first power supply voltage in response to a first output value of the comparator, and adjusting the second power supply voltage in response to a second output value of the comparator.

公开(公告)号：US09704967B2

公开(公告)日：2017-07-11

申请号：US14853719

申请日：2015-09-14

Applicant: STMicroelectronics S.A.

Inventor： Pascal Chevalier ,  Didier Celi ,  Jean-Pierre Blanc ,  Alain Chantre

IPC: H01L29/66 ,  H01L21/82 ,  H01L29/737 ,  H01L21/8249 ,  H01L27/06

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66325 ,  H01L29/737 ,  H01L29/7378

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

公开(公告)号：US09582675B2

公开(公告)日：2017-02-28

申请号：US14871873

申请日：2015-09-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Albert Martinez ,  William Orlando

IPC: G06F21/62 ,  G06F12/14 ,  G06F21/52 ,  G06F21/79 ,  G06F21/60

CPC classification number: G06F21/62 ,  G06F12/1408 ,  G06F12/1483 ,  G06F21/52 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2105

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Abstract translation: 一种用于将包含在至少第一存储器中的程序加载到执行单元可访问的第二存储器中的方法，其中程序处于第一存储器中的加密形式，用于控制对第二存储器的访问的电路是 由程序初始化数据，程序的指令，以及至少初始化数据被解密以在电路配置之后被传送到第二存储器中。