公开(公告)号：US09343506B2

公开(公告)日：2016-05-17

申请号：US14295770

申请日：2014-06-04

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666

Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.

Abstract translation: 一些实施例包括具有沿着第一方向延伸的第一系列访问/感测线的存储器阵列，在第一系列存取/检测线上的第二系列存取/感测线，并且沿着基本上与第 第一方向和存储单元在第一和第二系列访问/感测线之间垂直。 每个存储单元通过来自第一系列的访问/感测线和来自第二系列的访问/感测线的组合唯一地寻址。 存储单元具有可编程材料。 每个存储单元内的可编程材料中的至少一些是具有沿着不同于第一和第二方向的第三方向延伸的侧壁的多边形结构。 一些实施例包括形成存储器阵列的方法。

公开(公告)号：US20160056208A1

公开(公告)日：2016-02-25

申请号：US14468036

申请日：2014-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Andrea Ghetti

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

Abstract translation: 所公开的技术通常涉及集成电路器件，特别涉及交叉点存储器阵列及其制造方法。 形成线堆叠，包括设置在导线下方的存储材料线。 上导电线形成在线堆叠上并与线堆叠交叉，使相邻的上导线之间的线堆叠的部分暴露。 在形成上导线之后，通过从线堆叠的暴露部分去除存储材料，使得每个存储元件被空间横向包围，在下导电线和上导线之间的交叉处形成存储元件。 连续的密封材料横向围绕每个存储元件。

公开(公告)号：US09263674B2

公开(公告)日：2016-02-16

申请号：US14303652

申请日：2014-06-13

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Hernan A. Castro ,  Eddie T. Flores

IPC: H01L45/00 ,  H01L27/24 ,  H01L27/10 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L45/1273 ,  H01L21/32134 ,  H01L21/76838 ,  H01L27/101 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.

Abstract translation: 提供了使用蚀刻偏压均化形成的方法和存储器件。 使用蚀刻偏压均化形成存储器件的一个示例性方法包括在衬底上形成相应电平的导电材料。 在对相应级别的导电材料进行图案化期间，每个相应级别的导电材料电耦合到衬底上的对应电路，使得每个相应级别的导电材料在其图案化期间具有均质化的蚀刻偏压。 电耦合到衬底上的对应电路的每个相应级别的导电材料被图案化。

公开(公告)号：US20150357380A1

公开(公告)日：2015-12-10

申请号：US14295770

申请日：2014-06-04

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666

Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.

Abstract translation: 一些实施例包括具有沿着第一方向延伸的第一系列访问/感测线的存储器阵列，在第一系列存取/检测线上的第二系列存取/检测线，并且沿着基本上与第 第一方向和存储单元在第一和第二系列访问/感测线之间垂直。 每个存储单元通过来自第一系列的访问/感测线和来自第二系列的访问/感测线的组合唯一地寻址。 存储单元具有可编程材料。 每个存储单元内的可编程材料中的至少一些是具有沿着不同于第一和第二方向的第三方向延伸的侧壁的多边形结构。 一些实施例包括形成存储器阵列的方法。

公开(公告)号：US20150294716A1

公开(公告)日：2015-10-15

申请号：US14251002

申请日：2014-04-11

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0057

Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of reading memory cells in a memory array, such as a cross point memory array. In one aspect, the method comprises providing a memory array comprising a memory cell in one of a plurality of states. The method additionally comprises determining whether a threshold voltage (Vth) of the memory cell has a value within a predetermined read voltage window. A test pulse is applied to the memory cell if it is determined that the threshold voltage has a value within the predetermined read voltage window. The state of the memory cell may be determined based on a response of the memory cell to the test pulse, wherein the state corresponds to the one of the pluralities of states of the memory cell prior to receiving the test pulse.

Abstract translation: 所公开的技术通常涉及其操作的存储装置和方法，更具体地涉及读取存储器阵列（诸如交叉点存储器阵列）中的存储器单元的存储器阵列和方法。 在一个方面，所述方法包括提供包括以多种状态之一的存储器单元的存储器阵列。 该方法还包括确定存储器单元的阈值电压（Vth）是否具有在预定读取电压窗口内的值。 如果确定阈值电压具有预定读取电压窗口内的值，则将测试脉冲施加到存储器单元。 可以基于存储器单元对测试脉冲的响应来确定存储器单元的状态，其中该状态在接收测试脉冲之前对应于存储单元的多个状态中的一个状态。

公开(公告)号：US09112150B2

公开(公告)日：2015-08-18

申请号：US13948980

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Abstract translation: 一些实施例包括形成存储器单元的方法。 加热器结构形成在电节点阵列上，相变材料跨过加热器结构形成。 相变材料被图案化成多个限制结构，其中限制结构与加热器结构一一对应，并且通过一个或多个完全横向围绕每个限制结构的绝缘材料彼此间隔开 。 一些实施例包括在电节点阵列上具有加热器结构的存储器阵列。 密闭相变材料结构在加热器结构之上，并且与加热器结构一一对应。 受限制的相变材料结构通过一个或多个完全横向围绕每个限定相变材料结构的绝缘材料彼此间隔开。

公开(公告)号：US20150144864A1

公开(公告)日：2015-05-28

申请号：US14611011

申请日：2015-01-30

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

Abstract translation: 一些实施例包括形成存储器单元的方法。 堆叠包括在导电区域上的超声波材料。 堆叠被图案化成沿着第一方向延伸的轨道。 轨道被图案化为支柱。 导电线形成在超声波材料上。 导电线沿着与第一方向相交的第二方向延伸。 导电线沿着第二方向互连柱。 一些实施例包括具有沿着第一方向延伸的第一导电线的存储器阵列。 这些线包含半导体材料的n型掺杂区域。 支柱超过第一导线，并且包含n型掺杂区域的台面以及p型掺杂区域和超声材料。 第二导电线在超声波材料之上并且沿与第一方向相交的第二方向延伸。 第二导电线沿着第二方向互连柱。

公开(公告)号：US20150108422A1

公开(公告)日：2015-04-23

申请号：US14578704

申请日：2014-12-22

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Marcello Mariani ,  Giorgio Servalli

IPC: H01L27/24 ,  H01L29/732 ,  H01L21/762 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L45/00 ,  H01L29/66

CPC classification number: H01L27/2463 ,  H01L21/0338 ,  H01L21/76224 ,  H01L27/1022 ,  H01L27/2445 ,  H01L29/0649 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

Abstract: A method and resulting structure, is disclosed to fabricate vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a at least one dimension below the minimum lithographical resolution, F, of the lithographic technique employed. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.

Abstract translation: 公开了一种制造垂直双极结型晶体管的方法和结果，其包括基底接触柱和发射极接触柱的规则阵列，其具有低于采用的光刻技术的最小光刻分辨率F的至少一个维度。 诸如相变存储元件的存储元件可以形成在基底接触柱和发射极接触柱的规则阵列上方。

公开(公告)号：US08975148B2

公开(公告)日：2015-03-10

申请号：US13974641

申请日：2013-08-23

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

IPC: G11C17/16 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

Abstract: Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

Abstract translation: 一些实施例包括形成存储器单元的方法。 堆叠包括在导电区域上的超声波材料。 堆叠被图案化成沿着第一方向延伸的轨道。 轨道被图案化为支柱。 导电线形成在超声波材料上。 导电线沿着与第一方向相交的第二方向延伸。 导电线沿着第二方向互连柱。 一些实施例包括具有沿着第一方向延伸的第一导电线的存储器阵列。 这些线包含半导体材料的n型掺杂区域。 支柱超过第一导线，并且包含n型掺杂区域的台面以及p型掺杂区域和超声材料。 第二导电线在超声波材料之上并且沿与第一方向相交的第二方向延伸。 第二导电线沿着第二方向互连柱。

公开(公告)号：US20150044832A1

公开(公告)日：2015-02-12

申请号：US14491713

申请日：2014-09-19

Applicant: Micron Technology, Inc.

Inventor： Cristina Casellato ,  Carmela Cupeta ,  Michele Magistretti ,  Fabio Pellizzer ,  Roberto Somaschini

IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/101 ,  H01L27/24 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

Abstract translation: 电阻随机存取存储器可以包括存储器阵列和围绕存储器阵列的周边。 外围的解码器可以通过使用相同的金属沉积在同一时间在周边和阵列中形成金属化而耦合到阵列中的地址线。 金属化可以在阵列中形成行线。