中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

232 records (took 0.035 seconds)

    FRONT END RADIO ARCHITECTURE (FERA) WITH POWER MANAGEMENT
    222.
    发明申请
    FRONT END RADIO ARCHITECTURE (FERA) WITH POWER MANAGEMENT 有权
    前端无线电架构（FERA）与电源管理

    公开(公告)号：US20140038675A1

    公开(公告)日：2014-02-06

    申请号：US14051601

    申请日：2013-10-11

    Applicant: RF Micro Devices, Inc.

    Inventor： Nadim Khlat ,  Alexander Wayne Hietala

    IPC: H04W52/02

    CPC classification number: H04W52/0251 ,  H03F1/02 ,  H03F1/0227 ,  H03F3/24 ,  H03F3/68 ,  H03F3/72 ,  H03F2203/7209 ,  H03F2203/7221 ,  H04B1/0067 ,  H04B2001/045 ,  H04L5/001

    Abstract: A front end radio architecture (FERA) with power management is disclosed. The FERA includes a first power amplifier (PA) block having a first-first PA for amplifying first-first signals and a first-second PA for amplifying first-second signals. Also included is a second PA block having a second-first PA for amplifying second-first signals and a second-second PA for amplifying second-second signals. At least one power supply is adapted to selectively supply power to the first-first PA and the second-second PA through a first path. The power supply is also adapted to selectively supply power to the first-second PA and the second-first PA through a second path. A control system is adapted to selectively enable and disable the first-first PA, the first-second PA, the second-first PA, and the second-second PA.

    Abstract translation: 公开了具有电源管理的前端无线电架构（FERA）。 FERA包括具有用于放大第一信号的第一第一PA和用于放大第一秒信号的第一秒PA的第一功率放大器（PA）模块。 还包括具有用于放大第二第一信号的第二第一PA和用于放大第二秒信号的第二秒PA的第二PA块。 至少一个电源适于通过第一路径选择性地向第一首PA和第二秒PA供电。 电源还适于通过第二路径选择性地向第一和第二PA供电。 控制系统适于选择性地启用和禁用第一优先PA，第一秒PA，第二优先PA和第二秒PA。

    RF FRONT-END CIRCUITRY FOR RECEIVE MIMO SIGNALS
    224.
    发明申请
    RF FRONT-END CIRCUITRY FOR RECEIVE MIMO SIGNALS 有权
    用于接收MIMO信号的RF前端电路

    公开(公告)号：US20130337752A1

    公开(公告)日：2013-12-19

    申请号：US13943969

    申请日：2013-07-17

    Applicant: RF Micro Devices, Inc.

    Inventor： Nadim Khlat

    IPC: H04B1/44

    CPC classification number: H04B1/44 ,  B81B7/02 ,  H01P1/15

    Abstract: RF front-end circuitry arranged to provide for RF Multiple-Input and Multiple-Output (MIMO) signals is disclosed. In one embodiment, the RF front-end circuitry may include an antenna port, a first multiple throw (MT) switch, and a second MT switch. The first MT switch is configured to selectively couple a first pole port to any one of a first set of throw ports, and the second MT switch is configured to selectively couple a second pole port to any one of a second set of throw ports. The first pole port of the first MT switch is coupled to the antenna port. More than one of the second set of throw ports of the second MT switch are coupled to transmit one or more receive MIMO signals to RF transceiver circuitry. Accordingly, the RF front-end circuitry routes receive MIMO signals from the antenna port to the RF transceiver circuitry.

    Abstract translation: 布置成提供RF多输入和多输出（MIMO）信号的RF前端电路被公开。 在一个实施例中，RF前端电路可以包括天线端口，第一多掷（MT）开关和第二MT开关。 第一MT开关被配置为选择性地将第一极端口耦合到第一组投掷端口中的任何一个，并且第二MT开关被配置为选择性地将第二极端口耦合到第二组投掷端口中的任何一个。 第一MT开关的第一极端口耦合到天线端口。 第二MT开关的第二组投掷端口中的多于一个被耦合以将一个或多个接收MIMO信号传输到RF收发器电路。 因此，RF前端电路路由从天线端口接收MIMO信号到RF收发器电路。

    EXTRACTING CLOCK INFORMATION FROM A SERIAL COMMUNICATIONS BUS FOR USE IN RF COMMUNICATIONS CIRCUITRY
    225.
    发明申请
    EXTRACTING CLOCK INFORMATION FROM A SERIAL COMMUNICATIONS BUS FOR USE IN RF COMMUNICATIONS CIRCUITRY 有权
    从RF通信电路中使用的串行通信总线提取时钟信息

    公开(公告)号：US20130294554A1

    公开(公告)日：2013-11-07

    申请号：US13937307

    申请日：2013-07-09

    Applicant: RF Micro Devices, Inc.

    Inventor： Dharma Reddy Kadam ,  Christopher Truong Ngo ,  Nadim Khlat

    IPC: H04L7/04

    CPC classification number: H04L7/04 ,  G06F13/385 ,  H04J3/0685

    Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.

    Abstract translation: 本公开涉及包括多个RFFE电路的RF前端（RFFE）电路，每个RFFE电路可以由单独的集成电路（IC），前端模块或两者提供。 因此，RFFE电路可以使用RFFE串行通信总线彼此连接。 此外，一个或多个RFFE电路可能需要用于模数转换（ADC），数模转换（DAC），校准，传感器测量等的精确时钟源。 RFFE电路不是包含集成时钟源电路或者接收单独的外部时钟信号，而是可以从RFFE串行通信总线提取时钟信息以提供一个或多个时钟信号。 时钟信息可以经由RFFE串行通信总线与一个或多个串行通信命令相关联，可以与RFFE串行通信总线或两者的备用功能相关联。

    MULTI-MODE POWER AMPLIFIER ARCHITECTURE
    226.
    发明申请
    MULTI-MODE POWER AMPLIFIER ARCHITECTURE 有权
    多模式功率放大器架构

    公开(公告)号：US20130250820A1

    公开(公告)日：2013-09-26

    申请号：US13887965

    申请日：2013-05-06

    Applicant: RF Micro Devices, Inc.

    Inventor： Nadim Khlat

    IPC: H04L5/18

    CPC classification number: H04L5/18 ,  H04B1/0057 ,  H04L5/14

    Abstract: Radio frequency (RF) circuitry, which includes a time division duplex (TDD)/frequency division duplex (FDD) driver stage, a TDD final stage, an FDD final stage, and power directing circuitry, is disclosed. The power directing circuitry is coupled between the TDD/FDD driver stage and the TDD final stage, and is further coupled between the TDD/FDD driver stage and the FDD final stage.

    Abstract translation: 公开了包括时分双工（TDD）/频分双工（FDD）驱动器级，TDD最终级，FDD最后级和功率定向电路的射频（RF）电路。 功率引导电路耦合在TDD / FDD驱动级和TDD最终级之间，并且进一步耦合在TDD / FDD驱动级和FDD最后级之间。

    CARRIER AGGREGATION FRONT END ARCHITECTURE
    227.
    发明申请
    CARRIER AGGREGATION FRONT END ARCHITECTURE 有权
    承运人聚集前端建筑

    公开(公告)号：US20130250819A1

    公开(公告)日：2013-09-26

    申请号：US13848393

    申请日：2013-03-21

    Applicant: RF MICRO DEVICES, INC.

    Inventor： Nadim Khlat ,  Marcus Granger-Jones ,  Ruediger Bauder

    IPC: H04B1/10

    CPC classification number: H04B1/10 ,  H03H7/465 ,  H03H2007/013 ,  H03H2210/025 ,  H03H2210/033 ,  H03H2210/036 ,  H04L27/0002

    Abstract: Radio frequency (RF) front end circuitry includes a notch diplexer. The notch diplexer includes a high pass filter coupled between a high band port and an antenna port, and a low pass notch filter coupled between a low band port and the antenna port. The high pass filter is adapted to receive a high band receive signal having a high band carrier frequency at the antenna port, and pass the high band receive signal to the high band port. The low pass notch filter is adapted to receive a low band transmit signal having a low band carrier frequency at the low band port, and attenuate distortion in the low band transmit signal about a notch stop band before passing the low band transmit signal to the antenna port. According to one embodiment, the notch stop band includes the high band carrier frequency.

    Abstract translation: 射频（RF）前端电路包括一个切口双工器。 陷波分波器包括耦合在高频带端口和天线端口之间的高通滤波器以及耦合在低频带端口和天线端口之间的低通陷波滤波器。 高通滤波器适于在天线端口处接收具有高频带载波频率的高频带接收信号，并将高频带接收信号传送到高频带端口。 低通陷波滤波器适于在低频带端口接收具有低频带载波频率的低频带发射信号，并且在通过低频带发射信号到天线之前衰减低频带发射信号关于陷波阻挡带的失真 港口。 根据一个实施例，陷波阻挡带包括高频带载波频率。

    SHUNT SWITCH AT COMMON PORT TO REDUCE HOT SWITCHING
    228.
    发明申请
    SHUNT SWITCH AT COMMON PORT TO REDUCE HOT SWITCHING 有权
    在通用端口的分流开关减少热切换

    公开(公告)号：US20130207714A1

    公开(公告)日：2013-08-15

    申请号：US13764324

    申请日：2013-02-11

    Applicant: RF MICRO DEVICES, INC.

    Inventor： Ruediger Bauder ,  Nadim Khlat ,  Julio Costa ,  Jonathan Hammond

    IPC: B81B7/00

    CPC classification number: B81B7/0022 ,  B81B2201/014 ,  B81C1/00976 ,  H01H59/0009 ,  H04W52/02

    Abstract: Pilot switch circuitry grounds a hot node (an injection node) of a microelectromechanical system (MEMS) switch to reduce or eliminate arcing between a cantilever contact and a terminal contact when the MEMS switch is opened or closed. The pilot switch circuitry grounds the hot node prior to, during, and after the cantilever contact and terminal contact of the MEMS come into contact with one another (when the MEMS switch is closed). Additionally, the pilot switch circuitry grounds the hot node prior to, during, and after the cantilever contact and terminal contact of the MEMS disengage from one another (when the MEMS switch is opened).

    Abstract translation: 导向开关电路将微机电系统（MEMS）开关的热节点（注入节点）接地，以在MEMS开关打开或关闭时减少或消除悬臂触点和端子触点之间的电弧。 在MEMS悬臂接触之前，期间和之后，导频开关电路将热节点接地，并且MEMS的端子接触彼此接触（当MEMS开关闭合时）。 此外，导频开关电路在MEMS的彼此脱离接合之前，之中和之后，以及MEMS的彼此脱离接合（当MEMS开关断开时）接地。

    TUNABLE DUPLEXER ARCHITECTURE
    229.
    发明申请
    TUNABLE DUPLEXER ARCHITECTURE 有权
    TUNABLE双机架构

    公开(公告)号：US20130201880A1

    公开(公告)日：2013-08-08

    申请号：US13760159

    申请日：2013-02-06

    Applicant: RF MICRO DEVICES, INC.

    Inventor： Ruediger Bauder ,  Marcus Granger-Jones ,  Nadim Khlat

    IPC: H04L5/14

    CPC classification number: H04L5/14 ,  H03H7/48 ,  H04B1/44 ,  H04B1/525 ,  H04L25/03878

    Abstract: A tunable radio frequency (RF) duplexer is disclosed. The tunable RF duplexer includes a first hybrid coupler, a second hybrid coupler, and an RF filter circuit. The first hybrid coupler is operable to split an RF receive input signal into first and second RF quadrature hybrid receive signals (QHRSs). The first hybrid coupler is also operable to split an RF transmission input signal into first and second RF quadrature hybrid transmission signals (QHTSs). The RF filter circuit is operable to pass the first and second RF QHRSs to the second hybrid coupler and to reflect the first and second RF QHTSs back to the first hybrid coupler. Additionally, the second hybrid coupler is configured to combine the first and second RF QHRSs into an RF receive output signal, while the first hybrid coupler is configured to combine the first and second RF QHTSs into an RF transmission output signal.

    Abstract translation: 公开了一种可调谐射频（RF）双工器。 可调RF双工器包括第一混合耦合器，第二混合耦合器和RF滤波器电路。 第一混合耦合器可操作以将RF接收输入信号分成第一和第二RF正交混合接收信号（QHRS）。 第一混合耦合器还可操作以将RF传输输入信号分成第一和第二RF正交混合传输信号（QHTS）。 RF滤波器电路可操作以将第一和第二RF QHRS传递到第二混合耦合器并将第一和第二RF QHTS反射回第一混合耦合器。 此外，第二混合耦合器被配置为将第一和第二RF QHRS组合成RF接收输出信号，而第一混合耦合器被配置为将第一和第二RF QHTS组合成RF发射输出信号。

    VOLTAGE OFFSET LOOP FOR A SWITCHING CONTROLLER
    230.
    发明申请
    VOLTAGE OFFSET LOOP FOR A SWITCHING CONTROLLER 有权
    用于开关控制器的电压偏移环路

    公开(公告)号：US20130141064A1

    公开(公告)日：2013-06-06

    申请号：US13747749

    申请日：2013-01-23

    Applicant: RF Micro Devices, Inc.

    Inventor： Michael R. Kay ,  Nadim Khlat

    IPC: G05F1/46

    CPC classification number: G05F1/46 ,  H02M1/14 ,  H02M2001/0067 ,  H03F1/0227 ,  H03F1/26 ,  H03F3/24 ,  H03F2200/351 ,  H03F2200/451 ,  H03F2200/504 ,  H04B15/005

    Abstract: This disclosure relates to radio frequency (RF) power converters and methods of operating the same. In one embodiment, an RF power converter includes an RF switching converter, a low-drop out (LDO) regulation circuit, and an RF filter. The RF filter is coupled to receive a pulsed output voltage from the RF switching converter and a supply voltage from the LDO regulation circuit. The RF filter is operable to alternate between a first RF filter topology and a second RF filter topology. In the first RF filter topology, the RF filter is configured to convert the pulsed output voltage from a switching circuit into the supply voltage. The RF filter in the second RF filter topology is configured to filter the supply voltage from the LDO regulation circuit to reduce a ripple variation in a supply voltage level of the supply voltage. As such, the RF filter provides greater versatility.

    Abstract translation: 本公开涉及射频（RF）功率转换器及其操作方法。 在一个实施例中，RF功率转换器包括RF开关转换器，低压降（LDO）调节电路和RF滤波器。 RF滤波器被耦合以接收来自RF开关转换器的脉冲输出电压和来自LDO调节电路的电源电压。 RF滤波器可操作以在第一RF滤波器拓扑和第二RF滤波器拓扑之间交替。 在第一RF滤波器拓扑中，RF滤波器被配置为将来自开关电路的脉冲输出电压转换成电源电压。 第二RF滤波器拓扑中的RF滤波器被配置为对来自LDO调节电路的电源电压进行滤波，以减少电源电压的电源电压电平中的纹波变化。 因此，RF滤波器提供更大的通用性。

Patent Agency Ranking