公开(公告)号：US20210050369A1

公开(公告)日：2021-02-18

申请号：US17063397

申请日：2020-10-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11582 ,  H01L29/47 ,  H01L29/78 ,  H01L29/167 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/02 ,  H01L27/11578 ,  H01L29/792

Abstract: A 3D device, the device including: a first level including logic circuits; a second level including a plurality of dynamic memory cells; and a third level including a plurality of non-volatile memory cells, where the first level is bonded to the second level, and where the device includes refresh circuits to refresh the dynamic memory cells.

公开(公告)号：US10892016B1

公开(公告)日：2021-01-12

申请号：US16836659

申请日：2020-03-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11582

Abstract: A method to operate a 3D semiconductor charge trap memory device, the method comprising; executing a memory set-up operation, wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then executing a memory operation on said memory cells, wherein each memory cell of said plurality of memory cells comprises a charge trap layer, wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state. Various 3D devices, processing flows and methods are also disclosed.

公开(公告)号：US20200350310A1

公开(公告)日：2020-11-05

申请号：US16936352

申请日：2020-07-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Zeev Wurman

IPC: H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/84 ,  H01L23/48 ,  H01L23/544 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/812 ,  H01L29/423 ,  H01L29/732 ,  H01L29/808 ,  H01L21/768 ,  H01L21/822 ,  H01L23/367 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.

公开(公告)号：US20200335399A1

公开(公告)日：2020-10-22

申请号：US16916103

申请日：2020-06-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L27/105 ,  H01L21/683 ,  H01L23/525 ,  H01L21/84 ,  H03K19/17704 ,  H01L25/065 ,  H01L27/11 ,  H01L27/06 ,  H01L27/112 ,  G11C29/00 ,  H01L27/108 ,  H01L21/762 ,  H01L27/02 ,  H03K19/17764 ,  H01L23/544 ,  G11C16/04 ,  H01L29/78 ,  G11C17/14 ,  H03K17/687 ,  H01L25/18 ,  H03K19/17796 ,  H01L27/118 ,  G11C17/06 ,  H03K19/0948 ,  H01L29/786 ,  H01L27/092 ,  H01L23/36 ,  H03K19/17756 ,  H01L21/8238 ,  H01L27/11526 ,  G11C16/12 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/24 ,  H01L27/12 ,  G11C13/00

Abstract: A 3D semiconductor device including: a first level including first single crystal silicon and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors; a second level on top of the first metal layer, the second level including a plurality of second transistors; a third level on top of the second level, the third level including a plurality of third transistors; an oxide layer on top of the third level; a fourth level on top of the oxide layer, the fourth level including second single crystal silicon and many fourth transistors, where at least one of the plurality of second transistors is at least partially self-aligned to at least one of the plurality of third transistors, both being formed following the same lithography step, the fourth level is bonded to the oxide layer, the bonded includes many metal to metal bonded structures.

公开(公告)号：US20200321285A1

公开(公告)日：2020-10-08

申请号：US16907234

申请日：2020-06-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00

Abstract: A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.

公开(公告)号：US20200176420A1

公开(公告)日：2020-06-04

申请号：US16558304

申请日：2019-09-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/46 ,  H01L25/00

Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of RF circuits, and where a portion of interconnections between the plurality of logic circuits includes the RF circuits.

公开(公告)号：US20200013800A1

公开(公告)日：2020-01-09

申请号：US16526763

申请日：2019-07-30

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11582 ,  H01L23/528 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/10 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/311 ,  H01L21/321 ,  G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02 ,  H01L21/033 ,  H01L27/24 ,  H01L27/108 ,  G11C16/34

Abstract: A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.

公开(公告)号：US20190273121A1

公开(公告)日：2019-09-05

申请号：US16409813

申请日：2019-05-11

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L27/24 ,  H01L29/423 ,  H01L27/22 ,  H01L27/108 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L29/78 ,  H01L27/12 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11529

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.

公开(公告)号：US10388863B2

公开(公告)日：2019-08-20

申请号：US15452615

申请日：2017-03-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/108 ,  H01L21/762 ,  H01L27/06 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/00

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.

公开(公告)号：US10381328B2

公开(公告)日：2019-08-13

申请号：US15632325

申请日：2017-06-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/544 ,  H01L25/07 ,  H01L25/075

Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, and where the second die has a thickness of less than four microns.