公开(公告)号：US06967175B1

公开(公告)日：2005-11-22

申请号：US10726619

申请日：2003-12-04

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66818 ,  Y10S438/933

Abstract: A method of manufacturing a semiconductor device may include forming a fin on an insulator and forming a gate oxide on sides of the fin. The method may also include forming a gate structure over the fin and the gate oxide and forming a dielectric layer adjacent the gate structure. Material in the gate structure may be removed to define a gate recess. A width of a portion of the fin below the gate recess may be reduced, and a metal gate may be formed in the gate recess.

Abstract translation: 半导体器件的制造方法可以包括在绝缘体上形成翅片并在鳍的侧面形成栅极氧化物。 该方法还可以包括在鳍片和栅极氧化物上形成栅极结构，并形成与栅极结构相邻的电介质层。 可以去除栅极结构中的材料以限定栅极凹部。 可以减小栅极凹部下方的鳍的一部分的宽度，并且可以在栅极凹部中形成金属栅极。

公开(公告)号：US06960804B1

公开(公告)日：2005-11-01

申请号：US10633034

申请日：2003-10-10

Applicant: Chih-Yuh Yang ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Bin Yu

Inventor： Chih-Yuh Yang ,  Shibly S. Ahmed ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Bin Yu

IPC: H01L21/027 ,  H01L21/336 ,  H01L29/786 ,  H01L29/788

CPC classification number: H01L29/785 ,  H01L21/0276 ,  H01L29/42392 ,  H01L29/66795

Abstract: A double-semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The gate is formed on the insulating layer and surrounds the top surface, bottom surface and the side surfaces of the fin in the channel region of the semiconductor device. Surrounding the fin with gate material results in an increased total channel width and more flexible device adjustment margins.

Abstract translation: 双半导体器件包括衬底，绝缘层，鳍和栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 翅片具有多个侧表面，顶表面和底表面。 栅极形成在绝缘层上并且围绕半导体器件的沟道区域中的鳍的顶表面，底表面和侧表面。 用门材料围绕翅片会导致总通道宽度增加和设备调整裕度更灵活。

公开(公告)号：US06921963B2

公开(公告)日：2005-07-26

申请号：US10830006

申请日：2004-04-23

Applicant: Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

Inventor： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

Abstract: A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.

Abstract translation: 这里描述了窄通道FinFET，其具有窄的通道宽度。 可以在窄通道上形成保护层，保护层比窄通道宽。

公开(公告)号：US20050153485A1

公开(公告)日：2005-07-14

申请号：US10754540

申请日：2004-01-12

Applicant: Shibly Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/335

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.

Abstract translation: 形成鳍状场效应晶体管的方法包括：在鳍片的第一端上形成翅片并形成源极区域，在鳍片的第二端部形成漏极区域。 该方法还包括在鳍上形成具有第一图案的第一半导体材料的虚拟栅极，并在虚拟栅极周围形成介电层。 该方法还包括去除第一半导体材料以在对应于第一图案的电介质层中留下沟槽，使在沟槽内暴露的鳍片的一部分变薄，并在沟槽内形成金属栅极。

公开(公告)号：US20050121716A1

公开(公告)日：2005-06-09

申请号：US10726508

申请日：2003-12-04

Applicant: Wiley Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

Inventor： Wiley Hill ,  Haihong Wang ,  Yider Wu ,  Bin Yu

IPC: G11C16/04 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/785

Abstract: A memory device includes a conductive structure, a number of dielectric layers and a control gate. The dielectric layers are formed around the conductive structure and the control gate is formed over the dielectric layers. A portion of the conductive structure functions as a drain region for the memory device and at least one of the dielectric layers functions as a charge storage structure for the memory device. The dielectric layers may include oxide-nitride-oxide layers.

Abstract translation: 存储器件包括导电结构，多个电介质层和控制栅极。 电介质层形成在导电结构周围，并且控制栅极形成在电介质层上。 导电结构的一部分用作存储器件的漏极区，并且至少一个介电层用作存储器件的电荷存储结构。 电介质层可以包括氧化物 - 氮化物 - 氧化物层。

公开(公告)号：US06894355B1

公开(公告)日：2005-05-17

申请号：US10044493

申请日：2002-01-11

Applicant: Bin Yu ,  Olov Karlsson

Inventor： Bin Yu ,  Olov Karlsson

IPC: H01L21/28 ,  H01L27/01

CPC classification number: H01L21/28291

Abstract: A semiconductor device and method of manufacture. The semiconductor device having a silicide source and a silicide drain; a semiconductor body disposed between the source and the drain; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.

Abstract translation: 半导体器件及其制造方法。 具有硅化物源和硅化物漏极的半导体器件; 设置在源极和漏极之间的半导体本体; 栅电极，其设置在所述主体上并且限定插入在所述源极和所述漏极之间的沟道; 以及由高K材料制成并分离栅电极和主体的栅极电介质。

公开(公告)号：US06876042B1

公开(公告)日：2005-04-05

申请号：US10653105

申请日：2003-09-03

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A FinFET includes a fin formed on an insulating layer and a first gate material layer formed proximate to sides of the fin. The FinFET further includes a protective layer formed above the first gate material layer and the fin, and a second gate material layer formed above the protective layer and the fin. The second gate material layer may be formed into a gate for the fin that may be biased independently of gate(s) formed from the first gate material layer, thus providing additional design flexibility in controlling the potential in the fin during on/off switching of the FinFET.

Abstract translation: FinFET包括形成在绝缘层上的鳍和靠近鳍的侧面形成的第一栅极材料层。 FinFET还包括形成在第一栅极材料层和鳍上方的保护层，以及形成在保护层和鳍上方的第二栅极材料层。 第二栅极材料层可以形成为可以独立于由第一栅极材料层形成的栅极偏置的鳍的栅极，从而在控制鳍的电位的开/关切换期间提供额外的设计灵活性 FinFET。

公开(公告)号：US06855607B2

公开(公告)日：2005-02-15

申请号：US10459495

申请日：2003-06-12

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: C09G1/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

公开(公告)号：US06787439B2

公开(公告)日：2004-09-07

申请号：US10290276

申请日：2002-11-08

Applicant: Shibly S. Ahmed ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. An antireflective coating may be deposited on the planarized gate material, and a gate structure may be formed out of the planarized gate material using the antireflective coating.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构。 翅片结构可以包括侧表面和顶表面。 该方法还可以包括在鳍结构上沉积栅极材料并平坦化沉积的栅极材料。 可以在平坦化的栅极材料上沉积抗反射涂层，并且可以使用抗反射涂层从平坦化栅极材料形成栅极结构。

公开(公告)号：US06787402B1

公开(公告)日：2004-09-07

申请号：US09845604

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21355

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A double-gate vertical MOSFET transistor is described along with an associated fabrication method. The MOSFET transistor is configured with separate gates on each side of a vertical source-drain channel that is capped by an insulation layer. The fabrication process generally comprises forming a silicon-insulator stack having a silicon fin (channel) capped with insulation. The opposing ends of the silicon-insulator stack being configured with areas capable of receiving source and drain contacts. The vertical surfaces of the silicon fin are insulated prior to the formation of gate electrodes adjacent the two opposing sides of the silicon-insulator stack. By way of example, the gate electrodes are formed by depositing a thick layer of conductive gate material over the substrate and then removing the adjoining upper portion, such as by polishing. Portions of each gate electrode are configured with areas capable of receiving a gate contact.

Abstract translation: 描述双栅垂直MOSFET晶体管以及相关的制造方法。 MOSFET晶体管在垂直源极 - 漏极沟道的每一侧配置有分隔的栅极，该栅极被绝缘层封住。 制造工艺通常包括形成具有用绝缘体封盖的硅片（通道）的硅 - 绝缘体堆叠。 硅 - 绝缘体堆叠的相对端被配置有能够接收源极和漏极接触的区域。 在形成邻近硅 - 绝缘体堆叠的两个相对侧的栅电极之前，硅片的垂直表面被绝缘。 作为示例，栅电极通过在衬底上沉积厚的导电栅极材料层，然后例如通过抛光去除邻接的上部而形成。 每个栅电极的部分配置有能够接收栅极接触的区域。