公开(公告)号：US5717642A

公开(公告)日：1998-02-10

申请号：US803915

申请日：1997-02-25

Applicant: Luigi Pascucci ,  Carla Maria Golla

Inventor： Luigi Pascucci ,  Carla Maria Golla

IPC: G11C5/14 ,  G11C7/22 ,  G11C16/32 ,  G11C7/00

CPC classification number: G11C16/32 ,  G11C5/143 ,  G11C7/22

Abstract: A circuit for generating data load pulses of variable length as required includes a source for supplying a short load signal, and a delay element for generating longer pulses as of the short load signal. A static operating mode is provided wherein a load pulse is generated and maintained throughout static operation or as long as critical conditions (standby state, low voltage) persist. An extended pulse is always generated on exiting static operating mode; and the delay element may be disabled by a command when extended timing is not required.

Abstract translation: 根据需要产生可变长度的数据负载脉冲的电路包括用于提供短负载信号的源和用于从短负载信号产生较长脉冲的延迟元件。 提供静态操作模式，其中在静态操作期间或只要临界状态（待机状态，低电压）持续存在，就产生和维持负载脉冲。 总是在退出静态工作模式时产生扩展脉冲; 并且当不需要扩展定时时，延迟元件可能被命令禁用。

公开(公告)号：US5712776A

公开(公告)日：1998-01-27

申请号：US688296

申请日：1996-07-30

Applicant: Sergio Palara ,  Vito Graziano

Inventor： Sergio Palara ,  Vito Graziano

IPC: H02M7/5383 ,  H03K17/16 ,  H03K17/284 ,  H05B41/282 ,  H02M7/122

CPC classification number: H05B41/2825 ,  H02M7/5383 ,  H03K17/166 ,  H03K17/284

Abstract: A start up circuit causes a MOS transistor to be turned on by sensing local electrical quantities thereof, specifically the potential at the drain terminal of the MOS transistor. A small current is injected into the control terminal of the MOS transistor when the potential at the drain terminal is high. For the purpose, an electric network is arranged to couple these two terminals together.

Abstract translation: 启动电路通过感测其局部电量，特别是MOS晶体管的漏极端子处的电位，使MOS晶体管导通。 当漏极端子的电位高时，将小电流注入MOS晶体管的控制端。 为了这个目的，布置一个电网将这两个终端耦合在一起。

公开(公告)号：US5696399A

公开(公告)日：1997-12-09

申请号：US475555

申请日：1995-06-07

Applicant: Manlio Sergio Cereda ,  Giancarlo Ginami

Inventor： Manlio Sergio Cereda ,  Giancarlo Ginami

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H01L29/76

CPC classification number: H01L27/11526 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/823878 ,  H01L27/11546

Abstract: A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.

公开(公告)号：US5687124A

公开(公告)日：1997-11-11

申请号：US521304

申请日：1995-08-30

Applicant: Carla Golla ,  Silvia Padoan ,  Luigi Pascucci

Inventor： Carla Golla ,  Silvia Padoan ,  Luigi Pascucci

IPC: G11C17/00 ,  G11C7/00 ,  G11C16/02 ,  G11C16/34

CPC classification number: G11C16/3486 ,  G11C16/3459 ,  G11C16/3468

Abstract: A circuit for selectively programming a single bit in non-volatile memory is disclosed. The circuit consists of at least one comparator, at least one transistor, and at least one logic gate for each elementary memory in the memory word. In operation, the circuit allows for individual correction of mis-programmed cells within the memory by comparing the actual contents of the memory with the desired contents. If the actual contents does not match the desired contents, that individual cell is re-programmed.

Abstract translation: 公开了一种用于在非易失性存储器中选择性地编程单个位的电路。 电路由至少一个比较器，至少一个晶体管和至少一个逻辑门组成，用于存储器字中的每个基本存储器。 在操作中，电路允许通过将存储器的实际内容与期望的内容进行比较来对存储器内的错误编程的单元进行单独校正。 如果实际内容与所需内容不匹配，那么该单个单元格将被重新编程。

公开(公告)号：US5682349A

公开(公告)日：1997-10-28

申请号：US454650

申请日：1995-05-31

Applicant: Giovanni Campardo ,  Emilio Camerlenghi

Inventor： Giovanni Campardo ,  Emilio Camerlenghi

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  H01L27/00 ,  G11C11/34

CPC classification number: G11C29/82 ,  G11C16/34 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5006

Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults, such as low grain, in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

Abstract translation: 由于在正常操作期间发生诸如电池增益和电池排空的降低的故障现象，本发明提出在存储器件中，行和/或列地址解码装置（RDEC，CDEC）包括至少一个非易失性存储器（NVM ），并且读写控制逻辑（CL）包括被设计用于识别存储器件的矩阵（MAT）的行和/或列中的单元故障（例如低纹理）的装置（TST），并且写入 用于在与存在于矩阵（MAT）中的冗余行和/或列（RID）对应的正常操作地址期间在所述非易失性存储器（NVM）上写入的装置（WM），以纠正所述故障。

公开(公告)号：US5670904A

公开(公告)日：1997-09-23

申请号：US532016

申请日：1995-09-21

Applicant: David Moloney ,  Paolo Gadducci

Inventor： David Moloney ,  Paolo Gadducci

IPC: H03K5/13 ,  H03H11/26

CPC classification number: H03K5/131 ,  H03K5/133

Abstract: A programmable digital delay unit presenting a number of cascade-connected delay blocks, and a number of controlled bypass elements, one for each delay block. Each bypass element presents a bypass line and a multiplexer for selectively connecting the input or output of the respective delay block to the input of the next delay block. The delay blocks are formed by the cascade connection of flip-flops, and the number of flip-flops in each successive delay block, from the input of the delay unit, decreases in an arithmetic progression to the power of two, so that the selection signals for the respective multiplexers represent the bits of a digital word specifying the required delay.

Abstract translation: 一个可编程数字延迟单元，其呈现多个级联连接的延迟块，以及多个受控旁路元件，每个延迟块一个。 每个旁路元件呈现旁路线路和多路复用器，用于选择性地将相应延迟块的输入或输出连接到下一延迟块的输入端。 延迟块由触发器的级联连接形成，并且从延迟单元的输入端起的每个连续延迟块中的触发器的数量以算术级数减少到二的幂，使得选择 各个复用器的信号表示指定所需延迟的数字字的位。

公开(公告)号：US5670392A

公开(公告)日：1997-09-23

申请号：US498008

申请日：1995-06-30

Applicant: Giuseppe Ferla ,  Ferruccio Frisina

Inventor： Giuseppe Ferla ,  Ferruccio Frisina

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/66719 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66712 ,  Y10S148/126

Abstract: A process for manufacturing high-density MOS-technology power devices includes the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; forming an insulating material layer over the insulated gate layer; selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges, delimiting respective uncovered surface stripes of the semiconductor material layer; implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the insulating material layer to prevent the first dopant from being implanted in a central stripe of the uncovered surface stripes, to form pairs of heavily doped elongated source regions of the first conductivity type which extend along the two elongated edges of each elongated window and which are separated by the central stripe; implanting a low dose of a second dopant of a second conductivity type along two directions which lie in the plane, and which are substantially symmetrically tilted of a second prescribed angle with respect to the orthogonal direction, to form doped regions of the second conductivity type each comprising two lightly doped elongated channel regions extending under the two elongated edges of each elongated window; implanting a high dose of a third dopant of the second conductivity type substantially along the orthogonal direction, the insulating material layer acting as a mask, to form heavily doped regions substantially aligned with the edges of the elongated windows.

公开(公告)号：US5663681A

公开(公告)日：1997-09-02

申请号：US423565

申请日：1995-04-14

Applicant: Edoardo Botti ,  Giorgio Chiozzi

Inventor： Edoardo Botti ,  Giorgio Chiozzi

IPC: H03F1/30 ,  H03F3/181 ,  H03F3/72 ,  H03G3/34 ,  H03F1/26

CPC classification number: H03G3/348 ,  H03F1/305 ,  H03F3/72

Abstract: A low frequency amplifier comprising, in series, a first input stage, an intermediate amplifying stage and a final stage. The intermediate amplifying stage comprises a capacitor which is discharged when the amplifier is disabled, and is charged to a predetermined bias value when the amplifier is operative. To prevent voltage peaks at the output of the amplifier during the transient interval between the disabled and operating condition of the amplifier, a second input stage is provided which is only turned on during the transient interval, and is connected to the capacitor to detect its voltage and charge it. During the transient interval, the final stage is disabled. Upon the capacitor reaching the predetermined charge value, the second input stage practically turns itself off, and is then disabled; and, at the same time, the first input stage and the final stage are enabled to turn on the amplifier.

Abstract translation: 一种低频放大器，其包括串联的第一输入级，中间放大级和最后级。 中间放大级包括当放大器禁用时放电的电容器，并且当放大器工作时被充电到预定的偏置值。 为了防止在放大器的禁用和运行状态之间的瞬态间隔期间放大器输出端的电压峰值，提供了仅在瞬变间隔期间导通的第二输入级，并连接到电容器以检测其电压 并收取费用。 在瞬态间隔期间，最后一级被禁用。 当电容器达到预定电荷值时，第二输入级实际上自动关闭，然后禁用; 并且同时第一输入级和最后级都能够使放大器导通。

公开(公告)号：US5657276A

公开(公告)日：1997-08-12

申请号：US649468

申请日：1996-05-17

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0948 ,  G01R19/00

CPC classification number: G11C7/106 ,  G11C7/1051

Abstract: An output stage for integrated circuits, particularly for electronic memories, including: an input section that is adapted to acquire an input datum; a latch circuit having a first output and a second output and connected to the input section; a first inverter connected to the second output; a second inverter connected to the first output; a third inverter connected to the output of the second inverter; a grounding transistor driven by the second output of the latch circuit and adapted to connect the output of the third inverter to the ground; and a push-pull stage driven by the output of the first and third inverters. The output stage according to the present invention furthermore includes: a shorting transistor adapted to connect the output of the first inverter to the output of the second inverter; a first enabling transistor interposed between the first inverter and the first output of the latch circuit; a second enabling transistor interposed between the second inverter and the second output of the latch circuit; and a section for charging and discharging the push-pull stage, which is adapted to rapidly discharge the gate of the first transistor of the push-pull stage and to charge the gate of the second transistor of the push-pull stage during their operation.

Abstract translation: 一种用于集成电路的输出级，特别是用于电子存储器，包括：输入部分，其适于获取输入数据; 锁存电路，具有第一输出和第二输出并连接到输入部分; 连接到第二输出端的第一反相器; 连接到第一输出的第二反相器; 连接到第二反相器的输出的第三反相器; 由所述锁存电路的第二输出驱动并适于将所述第三反相器的输出连接到地的接地晶体管; 以及由第一和第三逆变器的输出驱动的推挽级。 根据本发明的输出级还包括：短路晶体管，其适于将第一反相器的输出连接到第二反相器的输出; 插入在第一反相器和锁存电路的第一输出端之间的第一使能晶体管; 插入第二反相器和锁存电路的第二输出之间的第二使能晶体管; 以及用于对推挽级充电和放电的部分，其适于快速放电推挽级的第一晶体管的栅极并且在其操作期间对推挽级的第二晶体管的栅极充电。

公开(公告)号：US5654861A

公开(公告)日：1997-08-05

申请号：US639345

申请日：1996-04-26

Applicant: Alessio Pennisi

Inventor： Alessio Pennisi

IPC: H02H5/04

CPC classification number: H02H5/044

Abstract: A bandgap type, thermal protection circuit for an integrated circuit does not require the use of a comparator and a voltage divider of the bandgap voltage. By contrast, the simplified thermal protection circuit of the invention utilizes a first transistor for mirroring the current flowing through the bandgap circuit through a second transistor that is functionally connected between the output node and ground. The control terminal of the second transistor is connected to a temperature dependent voltage derived from the bandgap circuit. The crossing point between the characteristic of such a temperature dependent voltage and of the VBE characteristic of the second transistor versus temperature determine the required transition on the output node.

Abstract translation: 用于集成电路的带隙型热保护电路不需要使用比较器和带隙电压的分压器。 相比之下，本发明的简化的热保护电路利用第一晶体管来镜像通过功能连接在输出节点和地之间的第二晶体管流过带隙电路的电流。 第二晶体管的控制端子连接到从带隙电路导出的与温度有关的电压。 这种温度相关电压的特性与第二晶体管的VBE特性对温度之间的交叉点决定了输出节点上所需的转换。