公开(公告)号：US20200335399A1

公开(公告)日：2020-10-22

申请号：US16916103

申请日：2020-06-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L27/105 ,  H01L21/683 ,  H01L23/525 ,  H01L21/84 ,  H03K19/17704 ,  H01L25/065 ,  H01L27/11 ,  H01L27/06 ,  H01L27/112 ,  G11C29/00 ,  H01L27/108 ,  H01L21/762 ,  H01L27/02 ,  H03K19/17764 ,  H01L23/544 ,  G11C16/04 ,  H01L29/78 ,  G11C17/14 ,  H03K17/687 ,  H01L25/18 ,  H03K19/17796 ,  H01L27/118 ,  G11C17/06 ,  H03K19/0948 ,  H01L29/786 ,  H01L27/092 ,  H01L23/36 ,  H03K19/17756 ,  H01L21/8238 ,  H01L27/11526 ,  G11C16/12 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/24 ,  H01L27/12 ,  G11C13/00

Abstract: A 3D semiconductor device including: a first level including first single crystal silicon and a plurality of first transistors; a first metal layer including interconnects between the plurality of first transistors; a second level on top of the first metal layer, the second level including a plurality of second transistors; a third level on top of the second level, the third level including a plurality of third transistors; an oxide layer on top of the third level; a fourth level on top of the oxide layer, the fourth level including second single crystal silicon and many fourth transistors, where at least one of the plurality of second transistors is at least partially self-aligned to at least one of the plurality of third transistors, both being formed following the same lithography step, the fourth level is bonded to the oxide layer, the bonded includes many metal to metal bonded structures.

公开(公告)号：US20200321285A1

公开(公告)日：2020-10-08

申请号：US16907234

申请日：2020-06-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00

Abstract: A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.

公开(公告)号：US20200176420A1

公开(公告)日：2020-06-04

申请号：US16558304

申请日：2019-09-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/46 ,  H01L25/00

Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of RF circuits, and where a portion of interconnections between the plurality of logic circuits includes the RF circuits.

公开(公告)号：US20200013800A1

公开(公告)日：2020-01-09

申请号：US16526763

申请日：2019-07-30

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/11582 ,  H01L23/528 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/10 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/311 ,  H01L21/321 ,  G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02 ,  H01L21/033 ,  H01L27/24 ,  H01L27/108 ,  G11C16/34

Abstract: A 3D memory device, the device including: a first horizontal bit-line; a second horizontal bit-line disposed above the first horizontal bit-line, where the first horizontal bit-line and the second horizontal bit-line function as a source or a drain for a plurality of parallel vertically-oriented memory transistors, where the first horizontal bit-line and the second horizontal bit-line are self-aligned being formed following the same lithography step; and conductive memory control lines, where a first portion of the conductive memory control lines are disposed at least partially directly underneath the plurality of parallel vertically-oriented memory transistors, and where a second portion of the conductive memory control lines are disposed at least partially directly above the plurality of parallel vertically-oriented memory transistors.

公开(公告)号：US20190273121A1

公开(公告)日：2019-09-05

申请号：US16409813

申请日：2019-05-11

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L27/24 ,  H01L29/423 ,  H01L27/22 ,  H01L27/108 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L29/78 ,  H01L27/12 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11529

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.

公开(公告)号：US10388863B2

公开(公告)日：2019-08-20

申请号：US15452615

申请日：2017-03-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/108 ,  H01L21/762 ,  H01L27/06 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/00

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.

公开(公告)号：US10381328B2

公开(公告)日：2019-08-13

申请号：US15632325

申请日：2017-06-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/544 ,  H01L25/07 ,  H01L25/075

Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, and where the second die has a thickness of less than four microns.

公开(公告)号：US20190244962A1

公开(公告)日：2019-08-08

申请号：US16377238

申请日：2019-04-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/10897 ,  H01L27/10802 ,  H01L27/10894 ,  H01L29/0649 ,  H01L29/7841

Abstract: A semiconductor device, the device including: a plurality of memory cells; and peripheral circuits, the peripheral circuits include controlling the plurality of memory cells, where each of the plurality of memory cells includes a first gate and a second gate, where the plurality of memory cells each include a channel region, at least one channel facet, a charge trap region and a tunneling region, where a portion of the peripheral circuits are designed to control the first gate and the second gate so to position two distinct memory sites, a first memory site and second a memory site, within the charge trap region of the at least one channel facet of at least one of the plurality of memory cells, and where the first memory site is substantially closer to the first gate than the second memory site.

公开(公告)号：US10325651B2

公开(公告)日：2019-06-18

申请号：US15494525

申请日：2017-04-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G11C13/00 ,  H01L27/24 ,  G11C29/00 ,  H01L45/00 ,  G11C11/404 ,  G11C11/4097 ,  H01L29/78 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11578 ,  H01L49/02 ,  G11C11/412 ,  G11C16/04

Abstract: A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.

公开(公告)号：US20190164834A1

公开(公告)日：2019-05-30

申请号：US16246412

申请日：2019-01-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L21/8238 ,  H03K19/177 ,  G11C16/04 ,  H01L27/105 ,  H01L29/78 ,  G11C17/14 ,  H01L21/683 ,  H01L27/108 ,  H01L23/525 ,  H01L21/84 ,  H03K17/687 ,  H01L25/18 ,  H01L25/065 ,  H01L27/11 ,  H01L27/112 ,  H01L27/118 ,  G11C17/06 ,  H01L27/06 ,  H03K19/0948 ,  H01L29/786 ,  H01L27/092 ,  H01L23/36 ,  G11C29/00 ,  H01L21/762 ,  H01L27/02 ,  H01L23/544

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells includes one first transistor, where each of the second memory cells includes one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, and where the forming at least one third level includes forming a window within the third level so to allow a lithography alignment through the third level to an alignment mark disposed underneath the third level.