公开(公告)号：US20230231022A1

公开(公告)日：2023-07-20

申请号：US17827994

申请日：2022-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L29/408 ,  H01L29/7786 ,  H01L29/66462 ,  H01L21/31155

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the barrier layer, a first layer adjacent to a first side of the p-type semiconductor layer without extending to a second side of the p-type semiconductor layer, and a second layer adjacent to the second side of the p-type semiconductor layer without extending to the first side of the p-type semiconductor layer.

公开(公告)号：US20230225221A1

公开(公告)日：2023-07-13

申请号：US18118669

申请日：2023-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chun-Hsien Lin

IPC: H01L27/22

CPC classification number: H10N50/80 ,  H10B61/00

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

公开(公告)号：US20230215801A1

公开(公告)日：2023-07-06

申请号：US17670520

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/7684 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76877

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

公开(公告)号：US20230207679A1

公开(公告)日：2023-06-29

申请号：US17577042

申请日：2022-01-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Ming Hou

IPC: H01L29/778 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/2003

Abstract: A complementary high electron mobility transistor includes an N-type HEMT and an P-type HEMT disposed on the substrate. The N-type HEMT includes a first undoped gallium nitride layer, a first quantum confinement channel, a first undoped group III-V nitride compound layer and an N-type group III-V nitride compound layer disposed from bottom to top. A first gate is disposed on the N-type group III-V nitride compound layer. A first source and a first drain are disposed at two sides of the first gate. The P-type HEMT includes a second undoped gallium nitride layer, a second quantum confinement channel, a second undoped group III-V nitride compound layer and a P-type group III-V nitride compound layer disposed from bottom to top. A second gate is disposed on the P-type group III-V nitride compound layer. A second source and a second drain are disposed at two sides of the second gate.

公开(公告)号：US20230207643A1

公开(公告)日：2023-06-29

申请号：US18113076

申请日：2023-02-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/408 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/66462

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer and includes a sunken surface, so as to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

公开(公告)号：US20230207620A1

公开(公告)日：2023-06-29

申请号：US17577403

申请日：2022-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Wei-Lun Huang ,  Chia-Wen Lu ,  Ta-Wei Chiu

IPC: H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/823481

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

公开(公告)号：US11690230B2

公开(公告)日：2023-06-27

申请号：US17345806

申请日：2021-06-11

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/80

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US20230200088A1

公开(公告)日：2023-06-22

申请号：US18113070

申请日：2023-02-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H10B61/00 ,  H01F41/34 ,  G11C11/16 ,  H01F10/32 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01F41/34 ,  G11C11/161 ,  H01F10/3254 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness

公开(公告)号：US20230197523A1

公开(公告)日：2023-06-22

申请号：US17586699

申请日：2022-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Chin-Hung Chen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/60

CPC classification number: H01L21/823456 ,  H01L27/0886 ,  H01L23/60 ,  H01L21/823431

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

公开(公告)号：US20230195989A1

公开(公告)日：2023-06-22

申请号：US17574527

申请日：2022-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Yen Tsai ,  Yi-Jung Chang

IPC: G06F30/392 ,  G06N20/10

CPC classification number: G06F30/392 ,  G06N20/10

Abstract: The invention provides an operation method of a semiconductor system, which includes providing a system which includes a layout pattern to scanning electron microscope (SEM) pattern prediction model (LS model) and a novelty detection model (ND model), inputting a layout pattern to the ND model, and the ND model judges whether the layout pattern is a novel layout pattern, and if the layout pattern is confirmed as the novel layout pattern after judgment, performing a process step on the novel layout pattern to form an SEM (scanning electron microscope) pattern.