公开(公告)号：US10606979B1

公开(公告)日：2020-03-31

申请号：US16001206

申请日：2018-06-06

Applicant: Xilinx, Inc.

Inventor： Shangzhi Sun ,  Bing Tian ,  Chaithanya Dudha

IPC: G06F17/50

Abstract: Verifying a circuit design may include, in response to modification of the circuit design involving at least one of inserting or removing a flip-flop, determining, using computer hardware, latency change values for pins of components of the circuit design, determining, using the computer hardware, total latency for the pins of the components of the circuit design based, at least in part, upon the latency change values, and comparing, using the computer hardware, total latency of the pins of the components of the circuit design. Verifying the circuit design may also include detecting, using the computer hardware, a latency error within the circuit design based upon the comparing and generating, using the computer hardware, a notification of the latency error in the circuit design, wherein the notification specifies a type of the latency error detected.

公开(公告)号：US20200099416A1

公开(公告)日：2020-03-26

申请号：US16142295

申请日：2018-09-26

Applicant: Xilinx, Inc.

Inventor： Christopher H. Dick ,  Hongzhi Zhao ,  Hemang M. Parekh ,  Xiaohan Chen

IPC: H04B3/06 ,  H04B1/04 ,  H04L25/03 ,  H04N7/10

Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some embodiments, a non-linear datapath is coupled to the input, where the non-linear datapath includes a plurality of parallel datapath elements each coupled to the input. By way of example, each of the plurality of parallel datapath elements is configured to add a different inverse non-linear component to the DPD input signal corresponding to a non-linear component of an amplifier. In various examples, a first combiner combines an output of each of the plurality of datapath elements to generate a first predistortion signal. In some embodiments, the DPD system further includes a linear datapath coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. In addition, a second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal.

公开(公告)号：US20200097038A1

公开(公告)日：2020-03-26

申请号：US15991179

申请日：2018-05-29

Applicant: Xilinx, Inc.

Inventor： Ryan Kinnerk ,  Bob W. Verbruggen ,  John E. McGrath

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/14

Abstract: Methods and apparatus for tracking delay in signals sent from a first clock domain to a second clock domain are disclosed. For example, at a first time a common timing reference signal (SysRef) may be received at the first clock domain, and a latency marker may be input into a first-in first-out data structure (FIFO) coupling the first clock domain to the second clock domain. At a second time, the SysRef may be received at the second clock domain, and a timer may be started at the second clock domain. At a third time, the latency marker may be received from the FIFO at the second clock domain, and the counter may be stopped at a final count. A FIFO latency may be determined based on the final count and on a difference between the second time and the first time.

公开(公告)号：US20200066713A1

公开(公告)日：2020-02-27

申请号：US16110894

申请日：2018-08-23

Applicant: Xilinx, Inc.

Inventor： Michael J. Hart ,  James Karp ,  Mohammed Fakhruddin ,  Pierre Maillard

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/73 ,  H01L29/78 ,  H01L49/02

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

公开(公告)号：US10574214B1

公开(公告)日：2020-02-25

申请号：US16137405

申请日：2018-09-20

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Yanran Chen ,  Michael J. Hart

IPC: H03K3/037 ,  H03K19/17764 ,  H03K19/1776 ,  H03K19/177 ,  H03K3/3562

Abstract: A circuit for storing data in an integrated circuit is described. The circuit comprises an input adapted to receive the data; a memory element coupled to the input, the memory element comprising a storage node for storing the data; at least one node that is separate from the storage node for storing the data; and at least a portion of a dummy transistor coupled to the at least one node that is separate from the storage node for storing the data. A method of storing data in an integrated circuit is also described.

公开(公告)号：US10572409B1

公开(公告)日：2020-02-25

申请号：US15976722

申请日：2018-05-10

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Ling Liu ,  Yifei Zhou ,  Ashish Sirasao

IPC: G06F3/00 ,  G06F5/00 ,  G06F13/20 ,  G06N3/08

Abstract: A memory arrangement can store a matrix of matrix data elements specified as index-value pairs that indicate row and column indices and associated values. First split-and-merge circuitry is coupled between the memory arrangement and a first set of FIFO buffers for reading the matrix data elements from the memory arrangement and putting the matrix data elements in the first set of FIFO buffers based on column indices. A pairing circuit is configured to read vector data elements, pair the vector data elements with the matrix data elements, and put the paired matrix and vector data elements in a second set of FIFO buffers based on column indices. Second split-and-merge circuitry is configured to read paired matrix and vector data elements from the second set of FIFO buffers and put the paired matrix and vector data elements in a third set of FIFO buffers based on row indices.

公开(公告)号：US10565346B1

公开(公告)日：2020-02-18

申请号：US15640009

申请日：2017-06-30

Applicant: Xilinx, Inc.

Inventor： Vishal Suthar ,  Dinesh D. Gaitonde ,  Amit Gupta ,  Jinny Singh

IPC: G06F17/50

Abstract: Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.

公开(公告)号：US20200042446A1

公开(公告)日：2020-02-06

申请号：US16053488

申请日：2018-08-02

Applicant: Xilinx, Inc.

Inventor： Millind Mittal ,  Jaideep Dastidar

IPC: G06F12/0815

Abstract: Circuits and methods for combined precise and imprecise snoop filtering. A memory and a plurality of processors are coupled to the interconnect circuitry. A plurality of cache circuits are coupled to the plurality of processor circuits, respectively. A first snoop filter is coupled to the interconnect and is configured to filter snoop requests by individual cache lines of a first subset of addresses of the memory. A second snoop filter is coupled to the interconnect and is configured to filter snoop requests by groups of cache lines of a second subset of addresses of the memory. Each group encompasses a plurality of cache lines.

公开(公告)号：US10545053B2

公开(公告)日：2020-01-28

申请号：US15616765

申请日：2017-06-07

Applicant: Xilinx, Inc.

Inventor： Umanath R. Kamath ,  Padraig Kelly ,  John K. Jennings

IPC: G01K7/00 ,  G01K7/01 ,  H03K19/003 ,  H03K19/0175 ,  G01K1/02

Abstract: An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

公开(公告)号：US20200026684A1

公开(公告)日：2020-01-23

申请号：US16041473

申请日：2018-07-20

Applicant: Xilinx, Inc.

Inventor： Ian A. Swarbrick ,  Sagheer Ahmad ,  Ygal Arbel ,  Dinesh D. Gaitonde

IPC: G06F15/78 ,  H04L12/24 ,  H04L12/933

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.