公开(公告)号：US11218137B2

公开(公告)日：2022-01-04

申请号：US16847807

申请日：2020-04-14

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uttam Saha ,  Mahbub Rashed

IPC: H03K3/037 ,  H03K19/20

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a low clock load dynamic dual output latch circuit and methods of operation. The structure includes: a plurality of dynamic clocked stacks which are configured to receive input data and provide a true logical value and a complement logical value; and a plurality of holding stacks which are configured to provide a hold signal to the dynamic clocked stacks and output the true logical value and the complement logical value in response to the hold signal being activated.

公开(公告)号：US11217584B2

公开(公告)日：2022-01-04

申请号：US16660868

申请日：2019-10-23

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Judson R. Holt ,  Jiehui Shu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L21/82 ,  H01L29/66

Abstract: A method limits lateral epitaxy growth at an N-P boundary area using an inner spacer. The method may include forming inner spacers on inner sidewalls of the inner active regions of a first polarity region (e.g., n-type) and an adjacent second polarity region (e.g., p-type) that are taller than any outer spacers on an outer sidewall of the inner active regions. During forming of semiconductor layers over the active regions (e.g., via epitaxy), the inner spacers abut and limit lateral forming of the semiconductor layers. The method generates larger semiconductor layers than possible with conventional approaches, and prevents electrical shorts between the semiconductor layers in an N-P boundary area. A structure includes the semiconductor epitaxy layers separated from one another, and abutting respective inner spacers. Any outer spacer on the inner active region is shorter than a respective inner spacer.

公开(公告)号：US11205701B1

公开(公告)日：2021-12-21

申请号：US16899086

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Henry Aldridge ,  John J. Ellis-Monaghan ,  Michel J. Abou-Khalil

IPC: H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is formed over a channel region of a substrate. A first source/drain region is positioned in the substrate adjacent to a first sidewall of the gate structure, a second source/drain region is positioned in the substrate adjacent to a second sidewall of the gate structure, and an extension region is positioned in the substrate. The extension region includes first and second sections that each overlap with the first source/drain region. The first and second sections of the extension region are spaced apart along a longitudinal axis of the gate structure. A portion of the channel region is positioned along the longitudinal axis of the gate structure between the first and second sections of the extension region.

公开(公告)号：US11205648B2

公开(公告)日：2021-12-21

申请号：US16866663

申请日：2020-05-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Elizabeth A. Strehlow ,  Harold Mendoza ,  Jay A. Mody ,  Clynn J. Mathew ,  Hong Yu ,  Yea-Sen Lin

IPC: H01L27/088 ,  H01L29/36 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8234

Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

公开(公告)号：US20210391489A1

公开(公告)日：2021-12-16

申请号：US16899028

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. LEVY ,  Siva P. ADUSUMILLI ,  Vibhor JAIN ,  John J. ELLIS-MONAGHAN

IPC: H01L31/107 ,  H01L31/0352 ,  H01L31/18

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

公开(公告)号：US20210391198A1

公开(公告)日：2021-12-16

申请号：US16901099

申请日：2020-06-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael Raga-Barone

IPC: H01L21/673

Abstract: An illustrative device disclosed herein includes a plate and a reticle pod receiving structure on the front surface of the plate that at least partially bounds a reticle pod receiving area on the front surface. In this example, the back surface of the plate has a pin engagement structure that is adapted to engage a plurality of pins and a fluid flow channel that is adapted to allow fluid communication with an interior region of a reticle pod when the reticle pod is positioned in the reticle pod receiving area.

公开(公告)号：US11195935B2

公开(公告)日：2021-12-07

申请号：US16531617

申请日：2019-08-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/266 ,  H01L27/11 ,  H01L21/3105 ,  H01L29/786 ,  H01L29/08 ,  H01L21/762

Abstract: A semiconductor device is disclosed including a gate electrode structure and raised drain and source regions that extend to a first height level and a sidewall spacer element positioned adjacent the sidewalls of the gate electrode structure between the raised drain and source regions and the gate electrode structure. The sidewall spacer element includes an upper portion that extends above the first height level wherein an inner part of the spacer element faces the gate electrode structure and extends to a second height level that is less than a third height level of an outer part of the upper portion of the spacer element.

公开(公告)号：US11195925B2

公开(公告)日：2021-12-07

申请号：US16732755

申请日：2020-01-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Qizhi Liu ,  Ramsey Hazbun ,  Pernell Dongmo ,  John J. Pekarik ,  Cameron E. Luce

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.

公开(公告)号：US20210376159A1

公开(公告)日：2021-12-02

申请号：US16890063

申请日：2020-06-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Mark Levy ,  Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/763

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

公开(公告)号：US20210376106A1

公开(公告)日：2021-12-02

申请号：US17404499

申请日：2021-08-17

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui SHU ,  Sipeng GU ,  Haiting WANG

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.