公开(公告)号：US20150123072A1

公开(公告)日：2015-05-07

申请号：US14555494

申请日：2014-11-26

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L27/24 ,  H01L27/108

CPC classification number: H01L27/2481 ,  H01L21/268 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L29/42392 ,  H01L29/7841 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L2029/7857 ,  H01L2221/6835

Abstract: A device, including: a first layer including first transistors and a second layer including second transistors, where at least one of the first transistors is self-aligned to one of the second transistors, where the second transistors are horizontally oriented transistors, and where the second layer includes a plurality of resistive-random-access memory (RRAM) cells, the memory cells including the second transistors.

Abstract translation: 一种器件，包括：包括第一晶体管的第一层和包括第二晶体管的第二层，其中所述第一晶体管中的至少一个与所述第二晶体管之一自对准，其中所述第二晶体管是水平取向的晶体管，并且其中 第二层包括多个电阻随机存取存储器（RRAM）单元，该存储单元包括第二晶体管。

公开(公告)号：US08921970B1

公开(公告)日：2014-12-30

申请号：US14198041

申请日：2014-03-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; where the second layer includes a through layer via with a diameter of less than 150 nm, and where at least one of the second transistors includes a back-bias structure.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 提供所述多个第一晶体管之间的互连的至少一个金属层; 第二层，包括多个第二晶体管，所述第二层覆盖所述至少一个金属层; 其中第二层包括具有小于150nm的直径的贯穿层通孔，并且其中至少一个第二晶体管包括背偏置结构。

公开(公告)号：US08846463B1

公开(公告)日：2014-09-30

申请号：US13902606

申请日：2013-05-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L21/84 ,  H01L21/8232

CPC classification number: H01L23/4827 ,  H01L21/268 ,  H01L21/302 ,  H01L21/76232 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8232 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/481 ,  H01L23/49827 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/1203 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/01066 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A method to construct a semiconductor device, the method including: forming a first mono-crystallized semiconductor layer; forming a second mono-crystallized semiconductor layer including mono-crystallized semiconductor transistors; where the second mono-crystallized semiconductor layer overlays the first mono-crystallized semiconductor layer, where the first mono-crystallized semiconductor layer includes an alignment mark and the transistors are aligned to the alignment mark, and where the first mono-crystallized semiconductor layer includes logic circuits, and connecting the logic circuits to an external device using input/output (I/O) circuits, where the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.

Abstract translation: 一种构造半导体器件的方法，所述方法包括：形成第一单结晶半导体层; 形成包括单结晶半导体晶体管的第二单结晶半导体层; 其中所述第二单结晶半导体层覆盖所述第一单结晶半导体层，其中所述第一单结晶半导体层包括对准标记，并且所述晶体管与所述对准标记对准，并且其中所述第一单结晶半导体层包括逻辑 电路，并且使用输入/输出（I / O）电路将逻辑电路连接到外部设备，其中输入/输出（I / O）电路构造在第二单结晶半导体层上。

公开(公告)号：US20250132187A1

公开(公告)日：2025-04-24

申请号：US18991504

申请日：2024-12-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/25 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H10D10/01 ,  H10D30/01 ,  H10D30/60 ,  H10D30/68 ,  H10D30/69 ,  H10D64/01 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D84/90 ,  H10D86/00 ,  H10D86/01 ,  H10D86/40 ,  H10D86/60 ,  H10D88/00 ,  H10D89/10

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.

公开(公告)号：US20250098325A1

公开(公告)日：2025-03-20

申请号：US18959033

申请日：2024-11-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  G03F9/00 ,  H01L21/268 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20

Abstract: A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.

公开(公告)号：US12199093B2

公开(公告)日：2025-01-14

申请号：US18668218

申请日：2024-05-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/06 ,  G03F9/00 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/367 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  H01L27/02 ,  H01L27/092 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B43/20 ,  H01L21/268 ,  H01L23/00 ,  H01L27/088

Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.

公开(公告)号：US20240395592A1

公开(公告)日：2024-11-28

申请号：US17942109

申请日：2022-09-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

Abstract: A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.

公开(公告)号：US20240379502A1

公开(公告)日：2024-11-14

申请号：US18778977

申请日：2024-07-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L21/74 ,  H01L23/34 ,  H01L23/50 ,  H01L23/544 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L27/118 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/78 ,  H01L29/808 ,  H10B12/00 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40 ,  H10B63/00

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.

公开(公告)号：US12144190B2

公开(公告)日：2024-11-12

申请号：US18677553

申请日：2024-05-29

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; and a second level including a plurality of second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of memory cells, where each of the plurality of memory cells includes at least one of the second transistors, where the device includes at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

公开(公告)号：US20240371906A1

公开(公告)日：2024-11-07

申请号：US18778976

申请日：2024-07-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/146

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.