公开(公告)号：US20240387219A1

公开(公告)日：2024-11-21

申请号：US18787755

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen Le LEE ,  Yen-Yu CHEN ,  Wei Chih CHEN ,  Tai Hsiang LIAO ,  Kai-Ping CHAN

IPC: H01L21/677

Abstract: An overhead transport vehicle is described for association with an Automated Material Handling System (AMHS). The overhead transport vehicle provides features to the AMHS by which the AMHS is able to reduce a number of manual urgent lot rescues by the fab operator when a logistic algorithm controlling traffic in the AMHS is unable to transport the front opening unified pods (FOUP) from one tool to the subsequent tool in the sequence of the process steps within the q-time due to unexpected problems. An indicator on the overhead transport vehicle which helps the fab operator with spotting a lot in trouble is described. A backup power source on the overhead transport vehicle used in case of a main power failure is also described.

公开(公告)号：US20240387188A1

公开(公告)日：2024-11-21

申请号：US18789319

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong TSAI ,  Ya-Lun CHEN ,  Tsai-Yu HUANG ,  Yahru CHENG ,  Huicheng CHANG ,  Yee-Chia YEO

IPC: H01L21/3105 ,  G03F7/16 ,  H01L21/027 ,  H01L21/311

Abstract: To reduce a thickness variation of a spin-on coating (SOC) layer that is applied over a plurality of first and second trenches with different pattern densities as a bottom layer in a photoresist stack, a two-step thermal treatment process is performed on the SOC layer. A first thermal treatment step in the two-step thermal treatment process is conducted at a first temperature below a cross-linking temperature of the SOC layer to cause flow of the SOC layer, and a second thermal treatment step in the two-step thermal treatment process is conducted at a second temperature to cause cross-linking of the SOC layer.

公开(公告)号：US20240387180A1

公开(公告)日：2024-11-21

申请号：US18787131

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Chou ,  Kuan-Yu Yeh ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L29/45

Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

公开(公告)号：US20240387178A1

公开(公告)日：2024-11-21

申请号：US18788563

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/28 ,  G03F7/09 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/02 ,  H01L21/027 ,  H01L21/30 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

公开(公告)号：US20240386176A1

公开(公告)日：2024-11-21

申请号：US18786780

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ta Lu ,  Chi-Ming Tsai

IPC: G06F30/39 ,  G06F111/06

Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

公开(公告)号：US20240385509A1

公开(公告)日：2024-11-21

申请号：US18320566

申请日：2023-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi YANG ,  Yao-Tang LIN ,  Zi-Wen CHEN ,  Jian-Yuan SU

IPC: G03F1/64 ,  G03F7/20 ,  G03F9/00

Abstract: A method includes: determining whether a first pellicle is to be inspected for inner particles; and in response to the first pellicle being to be inspected: forming a mask layer on a substrate; forming a defocused light path by shifting a mask assembly; exposing the mask layer by defocused light having a focal plane separated from the first pellicle by a distance; taking an image of the substrate; determining whether a threshold value is exceeded by analyzing the image; in response to the threshold value being exceeded, replacing the first pellicle with a second pellicle; and in response to the threshold value not being exceeded, processing production wafers using the first pellicle.

公开(公告)号：US20240385395A1

公开(公告)日：2024-11-21

申请号：US18467020

申请日：2023-09-14

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ming-Fa Chen ,  Shang-Yun Hou

IPC: G02B6/42

Abstract: In an embodiment, a method includes: forming an optical package, forming the optical package comprising: forming optical devices over a substrate; forming a first interconnect structure over the optical devices; and attaching a first semiconductor device to the optical devices; attaching a second semiconductor device to an interposer substrate; attaching the optical package to the interposer substrate; and attaching an optical port adjacent to the optical package, the optical port comprising: an optical fiber; and an optical redirection structure configured to redirect an optical signal between a first pathway and a second pathway, the first pathway being parallel with a major surface of the interposer substrate, the second pathway being non-parallel with the major surface of the interposer substrate.

公开(公告)号：US20240385370A1

公开(公告)日：2024-11-21

申请号：US18786711

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsuan Tai ,  Chung-Ming Weng ,  Hung-Yi Kuo ,  Cheng-Chieh Hsieh ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: G02B6/12 ,  G02B6/13 ,  G02B6/42 ,  G02B6/43 ,  H01L23/498

Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.

公开(公告)号：US20240383095A1

公开(公告)日：2024-11-21

申请号：US18786321

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chung CHEN ,  Yi-Shao LIN ,  Sheng-Tai PENG ,  Ya-Jen SHEUH ,  Hung-Lin CHEN ,  Ren-Dou LEE

IPC: B24B37/20 ,  B24B37/013 ,  B24B37/04 ,  C09G1/02

Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.

公开(公告)号：US12148828B2

公开(公告)日：2024-11-19

申请号：US17123982

申请日：2020-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Georgios Vellianitis ,  Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Mauricio Manfrini

IPC: H01L29/78 ,  H01L21/383 ,  H01L21/447 ,  H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate layer, a low-doping semiconductor layer, a crystalline ferroelectric layer and source and drain terminals. The crystalline ferroelectric layer is disposed between the gate layer and the low-doping semiconductor layer. The source terminal and the drain terminal are disposed on the low-doping semiconductor layer.