公开(公告)号：US10541934B1

公开(公告)日：2020-01-21

申请号：US15837400

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Ashish Banga

IPC: H04L12/863 ,  H04L12/947

Abstract: A network device includes a first port, a second port, a third port, and an arbitration circuit. The arbitration circuit is configured to receive a first frame and a second frame. The first frame is received from the first port and to be forwarded to the third port. The second frame is received from the second port and to be forwarded to the third port. The arbitration circuit compares a first priority of the first frame and a second priority of the second frame to generate a first comparison result. In response to the first comparison result, first forwarding data is generated based on the first and second frames. The first forwarding data is sent to an output of the arbitration circuit.

公开(公告)号：US10539610B2

公开(公告)日：2020-01-21

申请号：US15802253

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Mohsen H. Mardi ,  David M. Mahoney

IPC: G01R31/00 ,  G01R31/28 ,  G01R31/04

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.

公开(公告)号：US10528513B1

公开(公告)日：2020-01-07

申请号：US15967473

申请日：2018-04-30

Applicant: Xilinx, Inc.

Inventor： Chee Chong Chan ,  Warren E. Cory ,  Jason R. Bergendahl

IPC: G06F1/3296 ,  G06F13/40 ,  H03K19/0175 ,  G06F1/10 ,  G01R31/317 ,  G06F17/50

Abstract: An integrated circuit comprises programmable resources; a plurality of hard blocks; and a programmable connector coupled to the programmable resources, the plurality of hard blocks; wherein the programmable connector is configurable to route signals between a first hard block and a second hard block in a first mode of operation and to route signals between the first hard and the programmable resources in a second mode of operation.

公开(公告)号：US10515047B1

公开(公告)日：2019-12-24

申请号：US15982891

申请日：2018-05-17

Applicant: Xilinx, Inc.

Inventor： Pongstorn Maidee

IPC: G06F13/00 ,  G06F13/14 ,  G06F13/20 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: Apparatus and method relate to a data channel. In this apparatus, an input circuit is configured to gate a valid input with a ready output to provide a forward token (“f-token”) to a first f-token register of a f-token pipeline and to a counter, and to receive data to a first data register of a data pipeline. An output circuit is configured to gate a ready input with a valid output to provide a return token (“r-token”) to a first r-token register of a r-token pipeline and to a FWFT FIFO, to receive the f-token from a second f-token register of the f-token pipeline to the FWFT FIFO, and to receive the data from a second data register of the data pipeline to the FWFT FIFO. The input circuit receives the r-token from the first r-token register to a second r-token register of the r-token pipeline for the counter.

公开(公告)号：US10484012B1

公开(公告)日：2019-11-19

申请号：US15688628

申请日：2017-08-28

Applicant: Xilinx, Inc.

Inventor： Nihat E. Tunali ,  Richard L. Walke ,  Christopher H. Dick

IPC: H03M13/11

Abstract: A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.

公开(公告)号：US10482054B1

公开(公告)日：2019-11-19

申请号：US15261626

申请日：2016-09-09

Applicant: Xilinx, Inc.

Inventor： Ling Liu ,  Michaela Blott ,  Kimon Karras ,  Thomas Janson ,  Kornelis A. Vissers

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H04L12/861

Abstract: The coherent accelerator processor interface (CAPI) provides a high-performance when using heterogeneous compute architectures, but CAPI is not compatible with the advanced extensible interface (AXI) which is used by many accelerators. The examples herein describe an AXI-CAPI adapter (e.g., a hardware architecture) that converts AXI signals to CAPI signals and vice versus. In one example, the AXI-CAPI adapter includes four modules: a low-level shim, a high-level shim, an AXI full module, and an AXI Lite module which are organized in a hierarchy of hardware elements. Each of the modules outputs can output a different version of the AXI signals using the hierarchical structure.

公开(公告)号：US10468351B2

公开(公告)日：2019-11-05

申请号：US14469500

申请日：2014-08-26

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/07 ,  H01L23/16 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31

Abstract: Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.

公开(公告)号：US20190333892A1

公开(公告)日：2019-10-31

申请号：US15967109

申请日：2018-04-30

Applicant: Xilinx, Inc.

Inventor： Brian C. Gaide ,  Matthew H. Klein

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/535

Abstract: Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

公开(公告)号：US10437946B1

公开(公告)日：2019-10-08

申请号：US15255013

申请日：2016-09-01

Applicant: Xilinx, Inc.

Inventor： Amit Kasat ,  Shreegopal S. Agrawal ,  Venkat Prasad Aleti

IPC: G06F17/50

Abstract: Using pin planning for core sources includes identifying, using a processor, a first pin configuration and a second pin configuration for a core source of a behavioral description of a circuit design. The second pin configuration is generated by a pin planning operation. The first pin configuration of the core source can be compared with the second pin configuration of the core source using a processor. Responsive to detecting a difference between the first pin configuration and the second pin configuration, the core source can be automatically update, using the processor, based upon the second pin configuration.

公开(公告)号：US20190303762A1

公开(公告)日：2019-10-03

申请号：US16368945

申请日：2019-03-29

Applicant: Xilinx, Inc.

Inventor： Lingzhi SUI ,  Yushun WANG ,  Xin LIU

IPC: G06N3/08 ,  G06N3/04

Abstract: The present invention discloses a method to optimize a neural network computational graph. The computational graph is used for performing neural network calculation by a computational platform. The computational platform reads data needed by the calculation from off-chip memory. The method comprises: layers which can be fused are selected at least based on an optimization rule to reduce frequency of data exchange between the computational platform and the off-chip memory, carrying out fusion for at least two adjacent layers in the computational graph according to the selected layer objects. Here, the at least two adjacent layers are at least one of the following: horizontally adjacent layers having the same input of feature maps; and longitudinally adjacent layers in which the calculation results of a feature map of a previous layer are at least part of input for a next layer. The method to optimize a computational graph of the present invention can be automatically carried out based on rules or through isomorphic subgraph matching. Thus, an optimal reconstruction mode for executing the computational graph is found out, execution efficiency of the neural network computational platform is improved.