公开(公告)号：US10527670B2

公开(公告)日：2020-01-07

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US10539610B2

公开(公告)日：2020-01-21

申请号：US15802253

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Mohsen H. Mardi ,  David M. Mahoney

IPC: G01R31/00 ,  G01R31/28 ,  G01R31/04

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.

公开(公告)号：US20180284187A1

公开(公告)日：2018-10-04

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

CPC classification number: G01R31/2891 ,  G01R31/2889

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US09123738B1

公开(公告)日：2015-09-01

申请号：US14280223

申请日：2014-05-16

Applicant: Xilinx, Inc.

Inventor： David M. Mahoney ,  Mohsen H. Mardi

IPC: H01L23/58 ,  H01L21/44 ,  H01L23/66 ,  H01L21/768

CPC classification number: H01L23/66 ,  H01L21/76877 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2924/0002 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/4046 ,  H05K3/424 ,  H05K2201/09809 ,  H05K2203/308 ,  H01L2924/00

Abstract: In a transmission line via structure, a plurality of sub-structures are stacked in a via through the substrate along a longitudinal axis thereof. Each of the sub-structures includes a center conductor portion, an outer conductor portion, and at least one dielectric support member. The center conductor portion extends along the longitudinal axis. The outer conductor portion is disposed around the center conductor portion. The dielectric support member(s) separate the outer conductor portion and the center conductor portion and provide a non-solid volume between the outer conductor portion and the center conductor portion. Conductive paste is disposed between the center and outer conductor portions of successive ones of the plurality of sub-structures to form an outer conductor and a center conductor.

Abstract translation: 在传输线通孔结构中，多个子结构沿其纵轴通过基板堆叠在通孔中。 每个子结构包括中心导体部分，外部导体部分和至少一个电介质支撑部件。 中心导体部分沿着纵向轴线延伸。 外导体部设置在中心导体部周围。 电介质支撑构件将外部导体部分和中心导体部分分开，并在外部导体部分和中心导体部分之间提供非固体容积。 导电糊布置在多个子结构中的连续的子结构的中心和外导体部分之间以形成外部导体和中心导体。

公开(公告)号：US20190128950A1

公开(公告)日：2019-05-02

申请号：US15802251

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Mohsen H. Mardi ,  David M. Mahoney

IPC: G01R31/04 ,  G01R31/28

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress includes a plurality of pusher pins. The plurality of pusher pins have tips extending from a bottom surface of the workpress. Each of the plurality of pusher pins is configured to apply an independent and discrete force to the chip package assembly disposed in the socket.

公开(公告)号：US20170236809A1

公开(公告)日：2017-08-17

申请号：US15045228

申请日：2016-02-16

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger ,  Mohsen H. Mardi ,  David M. Mahoney

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.

公开(公告)号：US11043484B1

公开(公告)日：2021-06-22

申请号：US16362134

申请日：2019-03-22

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  James Karp ,  Siow Chek Tan ,  Martin L. Voogel ,  Mohsen H. Mardi ,  Suresh Ramalingam ,  David M. Mahoney

IPC: H01L27/02 ,  G01R1/04 ,  H01L25/065 ,  H01L23/498

Abstract: Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.

公开(公告)号：US10665579B2

公开(公告)日：2020-05-26

申请号：US15045228

申请日：2016-02-16

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger ,  Mohsen H. Mardi ,  David M. Mahoney

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/538 ,  H01L25/16 ,  H01L23/13

Abstract: A chip package assembly is provided that includes a substrate, at least one integrated circuit (IC) die and a power management integrated circuit (PMIC). In one example, the IC die of the chip package assembly is disposed on a first surface of the substrate. The PMIC die has a first surface having outputs electrically coupled to the second surface of the IC die. The PMIC die also has a second surface facing away from the first surface. The second surface of the PMIC die has inputs that are electrically coupled to the first surface of the substrate.

公开(公告)号：US10564212B2

公开(公告)日：2020-02-18

申请号：US15802251

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Mohsen H. Mardi ,  David M. Mahoney

IPC: G01R31/02 ,  G01R31/04 ,  G01R31/28

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress includes a plurality of pusher pins. The plurality of pusher pins have tips extending from a bottom surface of the workpress. Each of the plurality of pusher pins is configured to apply an independent and discrete force to the chip package assembly disposed in the socket.

公开(公告)号：US20190128956A1

公开(公告)日：2019-05-02

申请号：US15802253

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Mohsen H. Mardi ,  David M. Mahoney

IPC: G01R31/28 ,  G01R31/04

Abstract: An integrated chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an integrated circuit chip package test system includes a socket and a workpress. The socket is configured to receive a chip package assembly for testing in the test system. The workpress is positioned over the socket and has a bottom surface that is dynamically conformable to a multi-planar top surface topography of the chip package assembly.