公开(公告)号：US20250014649A1

公开(公告)日：2025-01-09

申请号：US18888899

申请日：2024-09-18

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G11C16/12 ,  G06F7/544 ,  G11C16/24 ,  G11C16/26

Abstract: An integrated circuit device having a mechanism to check calibration of memory cells configured to perform operations of multiplication and accumulation. The integrated circuit device programs, in a first mode, threshold voltages of first memory cells in a memory cell array to store weight data, and programs, in a second mode, threshold voltages of second memory cells in the memory cell array to store a first result of applying an operation of multiplication and accumulation to a sample input and the weight data. During a calibration check, the integrated circuit device performs the operation using the first memory cells to obtain a second result, and compares the first result, retrieved from the second memory cells, and the second result to determine whether calibration of output current characteristics of the first memory cells programmed in the first mode is corrupted.

公开(公告)号：US20250013716A1

公开(公告)日：2025-01-09

申请号：US18732881

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： William Charles Filipiak ,  Jeremy M. Hirst

IPC: G06F17/16 ,  G06N5/04

Abstract: Systems, methods, and apparatus related to memory devices that perform matrix vector multiplication using memory cells. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. A context of memory cells is determined by a controller (e.g., a memory controller internal or external to a memory chip having the array). The context can include, for example, a physical location of memory cells, weight patterns being programmed, and/or neighboring cell interference, etc. Based on the determined context, the controller dynamically determines adjustments (e.g., adjusted target threshold voltages or currents) for programming the memory cells to store weights prior to performing the matrix vector multiplication.

公开(公告)号：US20250013379A1

公开(公告)日：2025-01-09

申请号：US18773967

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Rakeshkumar Dayabhai Vaghasiya ,  Jameer Mulani ,  Anil Sindhi ,  Dhruv Chauhan

IPC: G06F3/06

Abstract: Techniques for memory operations are described. Indications of temperature levels at a memory device may be received, where each of the indications may be associated with a respective time point. Based on an indicated temperature level satisfying a first threshold, a derivative of a temperature of the memory device may be calculated using the indicated temperature levels. Based on calculating the derivative, a determination as to whether the derivative satisfies a second threshold may be determined. If the derivative satisfies the second threshold, operations for accessing the memory device may be modified. A second derivative of the temperature of the memory device may similarly be calculated and compared against a third threshold based on the indicated temperature level satisfying the first threshold. If the second derivative satisfies the third threshold, operations for accessing the memory device may be modified by a different amount.

公开(公告)号：US12191863B2

公开(公告)日：2025-01-07

申请号：US15956601

申请日：2018-04-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yantao Ma

IPC: H03K5/156

Abstract: Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. The duty cycle adjustment circuit may further be configured, after adjusting the duty cycle of the signal a first amount, to adjust the duty cycle of the signal a second amount different from the first amount using a fine adjustment to provide a duty cycle adjusted signal.

公开(公告)号：US12191284B2

公开(公告)日：2025-01-07

申请号：US18231192

申请日：2023-08-07

Applicant: Micron Technology, Inc.

Inventor： Pezhman Monadgemi

IPC: H01L25/065 ,  H01L25/00 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor device assembly comprises a substrate including internal contacts on a first side and first external contacts on a second side. The assembly further comprises one or more first dies disposed over the first side and electrically coupled to the internal contacts, and a interposer having a length and a width less than a length and a width of the substrate, having inner contacts on a first side, and having second external contacts on a second side. The interposer is coupled to the second side of the substrate by one or more of the inner contacts. The assembly further comprises a second die disposed between the substrate and the interposer. The assembly further comprises first solder balls on the first external contacts, and second solder balls on the second external contacts. The first and second solder balls are configured to bond with co-planar package contacts.

公开(公告)号：US12191249B2

公开(公告)日：2025-01-07

申请号：US17446868

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： David H. Wells ,  Richard J. Hill ,  Umberto M. Meotto ,  Matthew Thorum

IPC: H10B43/10 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/04

Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

公开(公告)号：US12190970B2

公开(公告)日：2025-01-07

申请号：US17824384

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Donghua Zhou

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/30

Abstract: A method includes determining a gap between a difference in a first health characteristic value and a second health characteristic value of blocks of memory cells and a health threshold associated with the blocks of memory cells, determining the gap is greater than or equal to a gap threshold from the health threshold, performing a pseudo media management operation on the blocks of memory cells, and determining an updated first health characteristic value of the blocks of memory cells.

公开(公告)号：US12189973B2

公开(公告)日：2025-01-07

申请号：US18101722

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F3/06

Abstract: A write command directed to a target zone of a memory device is received. Responsive to determining that a first portion of the target zone is open, the write command is executed at the first portion. Responsive to determining that the first portion has reached a threshold capacity, a second portion allocated to a media management pool is identified. The second portion satisfies a threshold capacity. One or more blocks associated with the second portion are erased. The second portion is allocated to a free block list.

公开(公告)号：US12189949B2

公开(公告)日：2025-01-07

申请号：US18049121

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Tommaso Vali ,  Walter Di Francesco ,  Luigi Pilolli ,  Angelo Covello ,  Andrea D'Alessandro ,  Agostino Macerola ,  Cristina Lattaro ,  Claudia Ciaschi

IPC: G06F3/06

Abstract: In some implementations, a memory device may receive a command to read data in a first format from non-volatile memory, the data being stored in a second format in the non-volatile memory, the second format comprising a plurality of copies of the data in the first format. The memory device may compare, using an error correction circuit, the plurality of copies of the data to determine a dominant bit state for bits of the data. The memory device may store the dominant bit state for bits of the data in the non-volatile memory as error-corrected data in the first format. The memory device may cause the error-corrected data to be read from the non-volatile memory in the first format as a response to the command to read the data in the first format.

公开(公告)号：US12189596B2

公开(公告)日：2025-01-07

申请号：US18532552

申请日：2023-12-07

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Brian Toronyi

IPC: G06F16/00 ,  G06F16/22

Abstract: A hash corresponding to a bit string is generated. The hash corresponds to an address location in a data structure associated with the bit string. An index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. In response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. In response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.