公开(公告)号：US20160020755A1

公开(公告)日：2016-01-21

申请号：US14796396

申请日：2015-07-10

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Matteo BELLITRA ,  Edoardo BOTTI

IPC: H03K5/003

CPC classification number: H03L5/00 ,  G05F1/613 ,  H03K5/003 ,  H03K19/00315

Abstract: An electronic device includes an output terminal, an output transistor having a control terminal and a conduction terminal coupled to the output terminal, and a resistor-capacitor (RC) compensation network configured to act on the control terminal of the output transistor. In addition, the electronic device includes a transconductance amplifier configured to drive the output terminal through the control terminal of the output transistor, and a Miller effect stage coupled to the RC compensation network and having an input port coupled to the transconductance amplifier and an output port coupled to the control terminal of the output transistor.

Abstract translation: 电子设备包括输出端子，具有控制端子和耦合到输出端子的导通端子的输出晶体管，以及被配置为作用于输出晶体管的控制端子的电阻 - 电容（RC）补偿网络。 此外，该电子设备包括跨导放大器，该跨导放大器经配置以通过输出晶体管的控制端驱动输出端，以及耦合到RC补偿网络的Miller效应级并具有耦合到跨导放大器的输入端口和输出端口 耦合到输出晶体管的控制端。

公开(公告)号：US20150318777A1

公开(公告)日：2015-11-05

申请号：US14644452

申请日：2015-03-11

Applicant: STMicroelectronics S.r.I

Inventor： Alfio Pasqua ,  Salvatore Tumminaro ,  Andrea Rapisarda

IPC: H02M1/36 ,  H02M3/335

CPC classification number: H02M3/33507 ,  H02M1/08 ,  H02M1/36 ,  H02M3/33515 ,  H02M3/33523 ,  H02M2001/0009 ,  H02M2001/0035 ,  Y02B70/16

Abstract: A switching converter converts an input signal to a regulated output signal using a switch and a transformer with a primary winding and a secondary winding. A wake up management circuit receives a transformer demagnetization signal and forces by wake up pulses the switch on when the switching converter operates in a burst mode. Sampled values of the transformer demagnetization signal are received. A setting circuit sets a first peak value of the current of the primary winding. A comparison circuit compare the sampled values with a voltage threshold and the preceding sampled value. In response thereto, the first peak value of the primary winding current is either maintained or a new peak value is set.

Abstract translation: 开关转换器使用开关和具有初级绕组和次级绕组的变压器将输入信号转换成稳定的输出信号。 唤醒管理电路通过唤醒脉冲接收变压器退磁信号，并在开关转换器以突发模式工作时接通。 接收变压器退磁信号的采样值。 设定电路设定初级绕组的电流的第一峰值。 比较电路将采样值与电压阈值和先前的采样值进行比较。 响应于此，初级绕组电流的第一峰值被保持或新的峰值被设定。

公开(公告)号：US09160236B2

公开(公告)日：2015-10-13

申请号：US13931564

申请日：2013-06-28

Applicant: STMicroelectronics S.r.I.

Inventor： Claudio Adragna ,  Claudio Spini ,  Aldo Vittorio Novelli ,  Fabrizio Bognanni

IPC: H02M3/335 ,  H02M3/337 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M3/33507 ,  H02M3/3376 ,  H02M2001/0035 ,  Y02B70/1433 ,  Y02B70/16

Abstract: An effective method enhances energy saving at low load in a resonant converter with a hysteretic control scheme for implementing burst-mode at light load. The method causes a current controlled oscillator of the converter to stop oscillating when a feedback control current of the output voltage of the converter reaches a first threshold value, and introduces a nonlinearity in the functional relation between the frequency of oscillation and said feedback control current or in a derivative of the functional relation, while the control current is between a lower, second threshold value and the first threshold value, such that the frequency of oscillation remains equal or smaller than the frequency of oscillation when the control current is equal to the second threshold value. Several circuital implementations are illustrated, all of simple realization without requiring any costly microcontroller.

Abstract translation: 一种有效的方法，在谐振转换器中，在负载较小的情况下，能够提供低负荷的节能，并采用迟滞控制方案，以实现轻载时的突发模式。 当转换器的输出电压的反馈控制电流达到第一阈值时，该方法使转换器的电流控制振荡器停止振荡，并且在振荡频率和所述反馈控制电流之间的功能关系中引入非线性，或 在所述功能关系的导数中，当所述控制电流在第二阈值和所述第一阈值之间时，使得当所述控制电流等于所述第二阈值时，所述振荡频率保持等于或小于所述振荡频率 阈值。 示出了几种电路实现，所有这些都是简单的实现，而不需要任何昂贵的微控制器。

公开(公告)号：US20150253268A1

公开(公告)日：2015-09-10

申请号：US14670613

申请日：2015-03-27

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Giovanni Girlando ,  Michele Calabretta ,  Francesco Pappalardo

IPC: G01N27/00 ,  G01M5/00

CPC classification number: G01N27/02 ,  G01M5/0033 ,  G01M5/0083 ,  G01N27/00 ,  H04Q9/00 ,  H04Q2209/88

Abstract: A monitoring device is for a block of building material. The monitoring device may include an electric supply line configured to be buried in the block of building material and having a flexible main cable, and flexible jumper cables coupled to the flexible main cable and extending outwardly. The monitoring device may include sensor devices configured to be buried in the block of building material and coupled to respective ones of the flexible jumper cables. Each sensor device may include a primary inductor coupled to the electric supply line at a position based upon peaks of a stationary waveform when the electric supply line is alternating current (AC) powered, and a monitoring circuit. The monitoring circuit may include an integrated sensor, and a secondary inductor magnetically coupled to the primary inductor and configured to supply the integrated sensor, and communicate through the electric supply line.

Abstract translation: 监测装置用于建筑材料块。 监测装置可以包括被配置为埋在建筑材料块中并具有柔性主电缆的电源线，以及耦合到柔性主电缆并向外延伸的柔性跳线。 监测装置可以包括被配置为埋在建筑材料块中并耦合到柔性跳线电缆中相应的一个的传感器装置。 每个传感器装置可以包括在电源线是交流（AC）供电时基于静止波形的峰值的位置处耦合到电源线的主电感器和监视电路。 监控电路可以包括集成传感器，以及次级电感器，其磁耦合到主电感器并且被配置为提供集成传感器，并且通过电源线进行通信。

公开(公告)号：US09128154B2

公开(公告)日：2015-09-08

申请号：US14496196

申请日：2014-09-25

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Franco Cesari

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/318552 ,  G01R31/318594

Abstract: An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer.

Abstract translation: 一个实施例涉及复杂多时钟域集成电路的扩展测试覆盖，而不需要结构化和可重复的标准方法，因此避免了定制解决方案并释放设计者来实现他的RTL代码，仅仅遵循由DFT识别的一般强制规则 工程师。 这种实施例通过在测试电路中引入与每个适当适配的时钟门控电路（OCC）接口的附加功能逻辑电路块（称为“片上时钟控制器”（icOCC））的实施例， 不同的时钟域。 icOCC启动不同OCC之间的同步，它们将来自外部ATE或ATPG工具的测试时钟信号和从内部at速度测试时钟发生器输出到不同时钟域的相应电路。 诸如OCC，扫描链等的扫描结构可以在门预扫描级别实例化，对由设计者编写的功能RTL代码具有低影响。

公开(公告)号：US20150221371A1

公开(公告)日：2015-08-06

申请号：US14605246

申请日：2015-01-26

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Luca Milani ,  Fabrizio Torricelli ,  Anna Richelli ,  Luigi Colalongo ,  Zsolt Miklos Kovàcs-Vajna

IPC: G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0408 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory includes memory cells arranged in rows and columns. Each memory cell includes a program/read portion and an erase portion that share an electrically floating layer of conductive material defining a first capacitive coupling with the program/read portion and a second capacitive coupling with the erase portion. The first capacitive coupling defines a first capacitance greater than a second capacitance defined by the second capacitive coupling. The erase portion is configured so that an electric current extracts charge carriers from the electrically floating layer to store a first logic value in the memory cell. The program/read portion is further configured so that an electric current injects charge carriers in the electrically floating layer to store a second logic value in the memory cell.

Abstract translation: 非易失性存储器包括以行和列排列的存储单元。 每个存储器单元包括程序/读取部分和擦除部分，其共享限定与程序/读取部分的第一电容耦合的导电材料的电浮置层和与擦除部分的第二电容耦合。 第一电容耦合限定大于由第二电容耦合限定的第二电容的第一电容。 擦除部分被配置为使得电流从电浮动层提取电荷载流子以将第一逻辑值存储在存储器单元中。 程序/读取部分被进一步配置成使得电流注入电浮置层中的电荷载流子以将第二逻辑值存储在存储单元中。

公开(公告)号：US20150219693A1

公开(公告)日：2015-08-06

申请号：US14615196

申请日：2015-02-05

Applicant: STMicroelectronics S.r.I.

Inventor： Dario Sutera ,  Davide Giuseppe Patti ,  Valeria Cinnera Martino

IPC: G01R15/20 ,  G01R19/00 ,  G01R15/18

CPC classification number: G01R15/202 ,  G01R15/18 ,  G01R15/207 ,  G01R19/0092 ,  G01R33/07

Abstract: The semiconductor integrated device has a conductive region, for example, an external contact pad, configured to be traversed by a current to be measured. A concentrator of magnetic material partially surrounds the conductive region and has an annular shape open at a point defining an air gap area where a sensitive region is arranged, which is electrically conductive and is typically of doped semiconductor material, such as polycrystalline silicon. The device is integrated in a chip formed by a substrate and by an insulating layer, the sensitive region and the concentrator being formed in the insulating layer.

Abstract translation: 半导体集成器件具有导电区域，例如外部接触焊盘，被配置为被被测量的电流穿过。 磁性材料的集中器部分地围绕导电区域并且具有在限定气隙区域的位置处的环形形状，其中布置有敏感区域，该敏感区域是导电的并且通常是掺杂半导体材料，例如多晶硅。 该器件集成在由衬底形成的芯片和绝缘层中，敏感区域和集中器形成在绝缘层中。

公开(公告)号：US09099516B2

公开(公告)日：2015-08-04

申请号：US13714013

申请日：2012-12-13

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe Scilla

IPC: H03K17/06 ,  H01L29/73 ,  H01L27/102 ,  H03K17/0812 ,  H03K17/082 ,  H03K17/12 ,  H03K17/14 ,  H01L27/02 ,  G01R19/00 ,  H01L29/06

CPC classification number: H01L29/73 ,  G01R19/0092 ,  H01L27/0207 ,  H01L27/1022 ,  H01L29/0692 ,  H01L29/7302 ,  H03K17/08126 ,  H03K17/0826 ,  H03K17/12 ,  H03K17/14 ,  H03K2217/0027

Abstract: A power bipolar structure is described having at least one first, one second and one third terminal and including at least one power bipolar transistor having a finger structure coupled to at least one driving block. The power bipolar transistor includes at least one elemental bipolar cell connected to these first, second and third terminals and including at least one power elemental bipolar structure corresponding to a finger of the power bipolar transistor, electrically coupled between the first and second terminals and coupled to a driving section of the driving block by at least one sensing section able to detect information on the operation of the power elemental bipolar structure, the sensing section being in turn coupled to a control circuit and supplying it with a current value as a function of the local temperature of the power elemental bipolar structure.

Abstract translation: 描述了具有至少一个第一，一个第二和一个第三端子的功率双极结构，并且包括具有耦合到至少一个驱动块的手指结构的至少一个功率双极晶体管。 功率双极晶体管包括连接到这些第一，第二和第三端子的至少一个元件双极单元，并且包括对应于功率双极晶体管的手指的至少一个功率元件双极结构，电耦合在第一和第二端子之间并耦合到 所述驱动块的驱动部分由至少一个感测部分能够检测关于所述功率元件双极结构的操作的信息，所述感测部分依次耦合到控制电路并将其作为所述功能元件双极结构的函数提供电流值 局部温度的功率元素双极结构。

公开(公告)号：US20150208557A1

公开(公告)日：2015-07-23

申请号：US14595391

申请日：2015-01-13

Applicant: STMICROELECTRONICS S.r.I. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Domenico Massimo PORTO ,  Giovanni Luca TORRISI ,  Sergio LECCE ,  Manuel GAERTNER

IPC: H05K7/20

CPC classification number: H05K7/20945 ,  H01L23/34 ,  H01L2924/0002 ,  H03K2017/0806 ,  Y10T307/773 ,  H01L2924/00

Abstract: A thermal control process for an electronic power device including a multi-junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.

Abstract translation: 包括多结集成电路的电子功率器件的热控制过程可以包括限定第一和至少一个第二组接点，每个组包括一个第一和至少一个第二结，并且将热检测器与每个 组。 可以执行第一组控制，其检测代表由热检测器检测到的温度的组电信号，参考组关键热事件处理组电信号，当对应的组电信号检测到关键组时识别临界组 并且产生适合于相对于集成电路的剩余结点选择性地去激活所识别的关键组的第一和至少一个第二结的组去激活信号。

公开(公告)号：US20150180528A1

公开(公告)日：2015-06-25

申请号：US14631397

申请日：2015-02-25

Applicant: STMicroelectronics S.r.I.

Inventor： Egidio Ragonese ,  Vincenzo Fiore ,  Nunzio Spina ,  Pierpaolo Lombardo ,  Giuseppe Palmisano

IPC: H04B1/40 ,  H04L27/08

CPC classification number: H04B1/40 ,  G08C19/02 ,  G08C19/16 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1296 ,  H03B2200/0074 ,  H04B3/54 ,  H04L27/08

Abstract: An apparatus includes first and second oscillator circuits. A transformer has a primary winding coupling the first oscillator circuit to the second oscillator circuit and a secondary winding. A first outgoing communications circuit is coupled to the second oscillator circuit and drives an amplitude modulated data signal thereto. A first incoming communications circuit is coupled to the primary winding of the transformer. A second outgoing communications circuit is coupled to the secondary winding drives an amplitude modulated data signal thereto. A second incoming communications circuit is coupled to the secondary winding. The secondary winding is magnetically coupled with the primary winding so the secondary winding receives an output power and an incoming data transmission based upon the amplitude modulated data signal, and so the primary winding receives an incoming high speed data transmission based upon the amplitude modulated data signal.

Abstract translation: 一种装置包括第一和第二振荡器电路。 变压器具有将第一振荡器电路耦合到第二振荡器电路的初级绕组和次级绕组。 第一输出通信电路耦合到第二振荡器电路并向其驱动调幅数据信号。 第一输入通信电路耦合到变压器的初级绕组。 耦合到次级绕组的第二输出通信电路驱动其幅度调制数据信号。 第二输入通信电路耦合到次级绕组。 次级绕组与初级绕组磁耦合，使得次级绕组基于幅度调制数据信号接收输出功率和输入数据传输，因此初级绕组基于幅度调制数据信号接收输入的高速数据传输 。