公开(公告)号：US20240431066A1

公开(公告)日：2024-12-26

申请号：US18340577

申请日：2023-06-23

Applicant: Intel Corporation

Inventor： Jeff Ku ,  Chi Chou Cheng ,  Jeffrey Ho ,  Chih-Tsung Hu ,  Srinivasarao Konakalla ,  Tsung-Kai Lin ,  Arnab Sen ,  Chiu-Chun Wang ,  Jiacheng Wu

IPC: H05K7/20 ,  G06F1/20

Abstract: Heat exchange apparatuses and methods for hyperbaric cooling fan applications such as computing devices. The apparatus comprises a material with high thermal conductivity and is configured to be overlaid on an internal surface of the housing, such that an internal surface of the apparatus is exposed to the hot air flowing inside the housing, and an external surface of the apparatus occludes at least some of the existing through-holes of the housing. In operation, the apparatus converts the through-holes into passive heat exchanging regions that passively transfer heat from inside the housing to outside the housing, which brings the internal air temperature and junction temperature (Tj) of the heat generating components down. Provided embodiments do not require reworking of the original industrial design (ID) of the housing.

公开(公告)号：US20240431061A1

公开(公告)日：2024-12-26

申请号：US18824590

申请日：2024-09-04

Applicant: Intel Corporation

Inventor： Alonso Rodriguez Chacon ,  Arturo Navarro Alvarez ,  Jeff Ku

IPC: H05K7/14 ,  H05K1/02

Abstract: Example fittings that combine standoffs and springs for supporting thermal solutions are disclosed herein. An example electronic device includes a chassis; a substrate; a thermal solution; and a fitting to separate the substrate from the chassis and to separate the thermal solution from the substrate, the fitting including a standoff end and a spring end.

公开(公告)号：US20240429816A1

公开(公告)日：2024-12-26

申请号：US18214031

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Nachiket Desai ,  Suhwan Kim

IPC: H02M3/155 ,  H02M1/088

Abstract: Some embodiments include an apparatus having a first node to receive a connection from a gate of a first transistor of a voltage converter; a second node to receive a connection from a gate of a second transistor of the voltage converter; a third node to receive a connection from a node between the first and second transistors; a capacitor including a first plate coupled to the third node; a first driver including an output node coupled to the first node, a first voltage node coupled to the first plate of the capacitor, and a second voltage node coupled to a second plate of the capacitor; a second driver including an output node coupled to the second node; and a circuit including third transistors coupled in series between the second voltage node and a third voltage node.

公开(公告)号：US20240429276A1

公开(公告)日：2024-12-26

申请号：US18212295

申请日：2023-06-21

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Shengsi Liu

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices having cells that include forksheet devices with source or drain regions of the same dopant type on both sides of the forksheet dielectric spine. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The forksheet devices may include all p-type source or drain regions on both sides of the dielectric spine or all n-type source or drain regions on both sides of the dielectric spine. Using forksheet devices with the same dopant type allows for both forksheet transistors and gate-all-around (GAA) transistors to be included within the same cell. The cell boundaries may also be placed along the forksheet dielectric spines rather than along gate cuts, which provides greater flexibility when designing multi-height cells.

公开(公告)号：US20240429269A1

公开(公告)日：2024-12-26

申请号：US18214244

申请日：2023-06-26

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Mamatha YAKKEGONDI VIRUPAKSHAPPA ,  Carla MORAN GUIZAN ,  Roshini SACHITHANANDAN ,  Philipp RIESS ,  Michael LANGENBUCH ,  Jonathan C. JENSEN

IPC: H01G4/30

Abstract: Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. A dielectric liner layer is between the alternating first metal lines and second metal lines and the metal plate.

公开(公告)号：US20240429238A1

公开(公告)日：2024-12-26

申请号：US18825952

申请日：2024-09-05

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Dax M. CRUM ,  Omair SAADAT ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

公开(公告)号：US20240428851A1

公开(公告)日：2024-12-26

申请号：US18212922

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Amlan GHOSH ,  Saroj SATAPATHY ,  Anandraj DEVARAJAN ,  Jaydeep KULKARNI ,  Feroze MERCHANT

IPC: G11C11/419 ,  G06F12/084 ,  G11C11/412

Abstract: Some embodiments relate generally to memory arrays having complementary bitlines. With some implementations, charge sharing to facilitate midrail read operations may be incorporated therein.

公开(公告)号：US20240427847A1

公开(公告)日：2024-12-26

申请号：US18757003

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE PARRA ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  SHUBRA MARWAHA ,  CHANDRA GURRAM ,  DARIN STARKEY ,  DURGESH BORKAR ,  VARGHESE GEORGE

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

Abstract: Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.

公开(公告)号：US20240427842A1

公开(公告)日：2024-12-26

申请号：US18674212

申请日：2024-05-24

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Fangwen Fu ,  Dhiraj D. Kalamkar ,  Sasikanth Avancha

IPC: G06F17/16 ,  G06F7/78 ,  G06F9/30 ,  G06N3/044 ,  G06N3/084

Abstract: An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.

公开(公告)号：US20240427728A1

公开(公告)日：2024-12-26

申请号：US18670721

申请日：2024-05-21

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.