公开(公告)号：US10651848B2

公开(公告)日：2020-05-12

申请号：US16290749

申请日：2019-03-01

Applicant: Rambus Inc.

Inventor： Huy Nguyen

IPC: H03K19/00 ,  H04L25/02 ,  H04B1/04

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

公开(公告)号：US10649930B2

公开(公告)日：2020-05-12

申请号：US16243055

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/02 ,  G11C7/10 ,  G06F12/06 ,  G11C7/20 ,  G11C7/22

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US20200117627A1

公开(公告)日：2020-04-16

申请号：US16601480

申请日：2019-10-14

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/362 ,  H01L27/02 ,  G11C16/26 ,  G11C16/10 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40 ,  H01L23/00 ,  H01L23/50 ,  G11C11/409 ,  G11C11/408 ,  H01L25/065 ,  H01L23/60 ,  H01L23/48

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

公开(公告)号：US10607669B2

公开(公告)日：2020-03-31

申请号：US15978344

申请日：2018-05-14

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  David Wang

IPC: G11C7/10 ,  G06F11/10 ,  G06F11/07 ,  G11C5/04 ,  G11C29/52 ,  G11C29/04

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US10600455B2

公开(公告)日：2020-03-24

申请号：US15916193

申请日：2018-03-08

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/06

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

公开(公告)号：US20200066314A1

公开(公告)日：2020-02-27

申请号：US16528523

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/08 ,  G11C7/22 ,  G11C7/12 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4076 ,  G11C5/02 ,  G11C7/08

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US10574734B2

公开(公告)日：2020-02-25

申请号：US15080371

申请日：2016-03-24

Applicant: Rambus Inc.

Inventor： Keith Lowery

IPC: H04L29/08

Abstract: Methods and systems for managing data storage and compute resources. The data can be stored a multiple locations allowing compute operations to be performed in a distributed manner in one or more locations. The cloud storage and cloud compute resources can be dynamically scaled based on the locations of the data and based on the cloud storage and/or cloud computing budgets. Dynamic reconfiguration of reconfigurable processors (e.g., FPGA) can further be used to accelerate compute operations.

公开(公告)号：US20200059263A1

公开(公告)日：2020-02-20

申请号：US16544475

申请日：2019-08-19

Applicant: Rambus Inc.

Inventor： Frederick Ware ,  Carl Werner

IPC: H04B3/32

Abstract: Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.

公开(公告)号：US10567683B2

公开(公告)日：2020-02-18

申请号：US15313029

申请日：2015-06-03

Applicant: Rambus Inc.

Inventor： Michael Guidash ,  John Ladd

IPC: H04N5/357 ,  H01L27/146 ,  H04N5/363 ,  H04N5/378

Abstract: A pixel circuit within an integrated-circuit image sensor includes a photodiode having a pinning layer of a first conductivity type, a floating diffusion node and a transfer gate disposed between the photodiode and the floating diffusion node. A first control input is coupled to the transfer gate, and a second control input is coupled to the pinning layer of the photodiode to enable the depletion potential of the photodiode to be raised and lowered.

公开(公告)号：US20200052873A1

公开(公告)日：2020-02-13

申请号：US16549303

申请日：2019-08-23

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian Leibowitz ,  Jaeha Kim ,  Jafar Savoj

IPC: H04L7/00 ,  H04L7/033 ,  G06Q10/10 ,  G06Q10/06 ,  H04L25/06

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.