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281.发明申请公开(公告)号：US20210005613A1
公开(公告)日：2021-01-07
申请号：US17026874
申请日：2020-09-21
Inventor： Abderrezak MARZAKI , Arnaud REGNIER , Stephan NIEL , Quentin HUBERT , Thomas CABOUT
IPC: H01L27/108 , H01L29/66 , H01L49/02 , H01L29/94
Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
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282.发明申请公开(公告)号：US20210005612A1
公开(公告)日：2021-01-07
申请号：US17026869
申请日：2020-09-21
Inventor： Abderrezak MARZAKI , Arnaud REGNIER , Stephan NIEL , Quentin HUBERT , Thomas CABOUT
IPC: H01L27/108 , H01L29/66 , H01L49/02 , H01L29/94
Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.
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公开(公告)号：US10833094B2
公开(公告)日：2020-11-10
申请号：US15954874
申请日：2018-04-17
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Fausto Piazza , Sebastien Lagrasta , Raul Andres Bianchi , Simon Jeannot
IPC: H01L27/11546 , H01L21/28 , H01L27/06 , H01L49/02 , H01L21/02 , H01L21/3205 , H01L21/3213 , H01L27/11521 , H01L29/49 , H01L29/66 , H01L21/8234 , H01L27/11541
Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
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公开(公告)号：US10833027B2
公开(公告)日：2020-11-10
申请号：US15784883
申请日：2017-10-16
Inventor： Mathieu Lisart , Raul Andres Bianchi , Benoit Froment
IPC: G01L23/00 , H01L23/00 , H04L9/32 , H04L9/00 , G06F9/4401 , H01L21/265 , H01L21/266 , H01L21/3205 , H01L21/8234 , H01L23/528 , H01L27/088 , H03K17/14
Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
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公开(公告)号：US10823986B2
公开(公告)日：2020-11-03
申请号：US16254798
申请日：2019-01-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Frédéric Boeuf
Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
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Patent Agency Ranking
公开(公告)号：US10804112B2
公开(公告)日：2020-10-13
申请号：US15979147
申请日：2018-05-14
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Loic Gaben
IPC: H01L21/306 , H01L21/02 , H01L21/311 , B81C1/00 , H01L21/321
Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.
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公开(公告)号：US10797234B2
公开(公告)日：2020-10-06
申请号：US16182990
申请日：2018-11-07
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Olivier Hinsinger
Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.
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公开(公告)号：US10771048B2
公开(公告)日：2020-09-08
申请号：US16747341
申请日：2020-01-20
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA
Inventor： Capucine Lecat-Mathieu De Boissac , Fady Abouzeid , Gilles Gasiot , Philippe Roche , Victor Malherbe
Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.
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公开(公告)号：US20200258981A1
公开(公告)日：2020-08-13
申请号：US16788091
申请日：2020-02-11
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Nicolas GUITARD
IPC: H01L29/08 , H01L29/167 , H01L29/66 , H01L29/74 , H01L27/102 , H01L27/02
Abstract: Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.
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公开(公告)号：US10714501B2
公开(公告)日：2020-07-14
申请号：US16057466
申请日：2018-08-07
Inventor： Jean-Jacques Fagot , Philippe Boivin , Franck Arnaud
IPC: H01L27/12 , H01L21/762 , H01L21/84 , H01L29/808 , H01L27/06
Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
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