公开(公告)号：US09812549B2

公开(公告)日：2017-11-07

申请号：US15257567

申请日：2016-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L21/3205 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L29/51

CPC classification number: H01L29/6653 ,  H01L21/28008 ,  H01L21/28247 ,  H01L21/31116 ,  H01L23/5226 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements. The method further includes partially removing the spacer elements such that an upper portion of the recess becomes wider. In addition, the method includes forming a metal gate stack in the recess and forming a protection element over the metal gate stack to fill the recess.

公开(公告)号：US20170316982A1

公开(公告)日：2017-11-02

申请号：US15646078

申请日：2017-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3083 ,  H01L21/311 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A substrate having a first area and a second area is provided. The substrate is patterned to form trenches in the substrate and semiconductor fins between the trenches, wherein the semiconductor fins comprises first semiconductor fins distributed in the first area and second semiconductor fins distributed in the second area. A first fin cut process is performed in the first area to remove portions of the first semiconductor fins. Insulators are formed in the trenches after the first fin cut process is performed. A second fin cut process is performed in the second area to remove portions of the second semiconductor fins until gaps are formed between the insulators in the second area. A gate stack is formed to partially cover the first semiconductor fins, the second semiconductor fins and the insulators.

公开(公告)号：US09793406B2

公开(公告)日：2017-10-17

申请号：US14925680

申请日：2015-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/7851 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.

公开(公告)号：US09780026B2

公开(公告)日：2017-10-03

申请号：US15131608

申请日：2016-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5329

Abstract: An interconnection structure includes a non-insulator structure, a liner layer, a dielectric structure and a conductive structure. The liner layer is present on the non-insulator structure and has an opening therein. The dielectric structure is present on the liner layer. The dielectric structure includes a via opening therein. The conductive structure is present in the via opening of the dielectric structure and electrically connected to the non-insulator structure through the opening of the liner layer. At least a portion of the conductive structure tapers along a direction from the non-insulator structure to the dielectric structure.

公开(公告)号：US09768168B2

公开(公告)日：2017-09-19

申请号：US14968917

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L29/49 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts with sidewalls of the opposite spacers.

公开(公告)号：US09704969B1

公开(公告)日：2017-07-11

申请号：US14985406

申请日：2015-12-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/30

CPC classification number: H01L29/66545 ,  H01L21/30 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/7856

Abstract: A semiconductor device including a substrate, a plurality of insulators, a dielectric layer and a plurality of gates is provided. The substrate includes a plurality of trenches and a semiconductor fin between trenches. The insulators are disposed in the trenches. The dielectric layer covers the semiconductor fin and the insulators. A lengthwise direction of the gates is different from a lengthwise direction of the semiconductor fin. The gates comprise at least one first gate that is penetrated by the semiconductor fin and at least one second gate that is not penetrated through by the semiconductor fin. The second gate comprises a broadened portion disposed on the dielectric layer and a top portion disposed on the broadened portion, wherein a bottom width of the broadened portion is greater than a width of the top portion.

公开(公告)号：US20170179241A1

公开(公告)日：2017-06-22

申请号：US14987598

申请日：2016-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/417 ,  H01L21/311 ,  H01L23/535 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/41775 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/7831 ,  H01L2221/1063

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

公开(公告)号：US20170179117A1

公开(公告)日：2017-06-22

申请号：US14987294

申请日：2016-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a core device, and an input/output (I/O) device. The core device is disposed on the substrate. The core device includes a first gate electrode having a bottom surface and at least one sidewall. The bottom surface of the first gate electrode and the sidewall of the first gate electrode intersect to form a first interior angle. The I/O device is disposed on the substrate. The I/O device includes a second gate electrode having a bottom surface and at least one sidewall. The bottom surface of the second gate electrode and the sidewall of the second gate electrode intersect to form a second interior angle greater than the first interior angle of the first gate electrode.

公开(公告)号：US09685554B1

公开(公告)日：2017-06-20

申请号：US15062215

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first ridge portion embedded in the first concave and the drain includes a second ridge portion embedded in the second concave, wherein the first and second ridge portions extend along a height direction of the semiconductor fin.

公开(公告)号：US20170170320A1

公开(公告)日：2017-06-15

申请号：US14968906

申请日：2015-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/785

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.