公开(公告)号：US06870427B2

公开(公告)日：2005-03-22

申请号：US10401510

申请日：2003-03-27

Applicant: Philippe Cathelin ,  Jean-Charles Grasset

Inventor： Philippe Cathelin ,  Jean-Charles Grasset

IPC: H03F1/30 ,  H03F1/32 ,  H03F3/04

CPC classification number: H03F1/302 ,  H03F1/32

Abstract: The operation of a bipolar transistor is controlled comprising by producing a first voltage that is a product of a static collector current of the bipolar transistor times an emitter resistance. The first voltage is then compared to a predetermined reference voltage to produce a control signal. Current is then injected a base of the bipolar transistor in response to the control signal. In a specific implementation, the first voltage, which is a product of the static collector current (Ic) of the bipolar transistor times its emitter resistance (RE) , is slaved to a predetermined reference voltage (Vref) whose value is substantially equal, to within a tolerance, to 13 mV at a temperature at or about 27° C.

Abstract translation: 控制双极晶体管的操作包括通过产生作为双极晶体管的静态集电极电流乘以发射极电阻的乘积的第一电压。 然后将第一电压与预定的参考电压进行比较以产生控制信号。 然后响应于控制信号将电流注入双极晶体管的基极。 在具体实施中，作为双极晶体管的静态集电极电流（Ic）乘以其发射极电阻（RE）的乘积的第一电压被驱动到其值基本相等的预定参考电压（Vref），相对于 在公差范围内，在或约27℃的温度下达到13mV

公开(公告)号：US06864898B1

公开(公告)日：2005-03-08

申请号：US09660850

申请日：2000-09-13

Applicant: Marc Laury ,  Franck Seigneret ,  Emmanuel Chiaruzzi

Inventor： Marc Laury ,  Franck Seigneret ,  Emmanuel Chiaruzzi

IPC: G06T5/20 ,  H04N1/60 ,  G09G5/00

CPC classification number: H04N1/6058 ,  G06T5/20

Abstract: A method of approximation of the respective colors of pixels of a digital image by selecting, from a look-up table and successively for each pixel of the image, a color, the code of which comes close with the smallest error to the sum of the code of the current pixel color and of a correction term, in which the correction term is equal to the smallest error calculated upon approximation of a preceding pixel, assigned with a weighting coefficient depending on the position of the current pixel in the image.

Abstract translation: 通过从查找表中选择并连续地针对图像的每个像素来逼近数字图像的各个颜色的颜色的方法，该颜色的代码以最小的误差接近于 当前像素颜色的代码和校正项，其中校正项等于根据先前像素的近似计算的最小误差，其被分配有取决于图像中的当前像素的位置的加权系数。

公开(公告)号：US06864542B2

公开(公告)日：2005-03-08

申请号：US10379169

申请日：2003-03-04

Applicant: Yvon Gris ,  Thierry Schwartzmann

Inventor： Yvon Gris ,  Thierry Schwartzmann

IPC: H01L21/761 ,  H01L21/762 ,  H01L21/8228 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/76

CPC classification number: H01L27/0826 ,  H01L21/761 ,  H01L21/76232 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0623

Abstract: A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.

Abstract translation: 一种在P型衬底中制造双极晶体管的方法，包括以下步骤：在衬底中形成第一N型区域; 通过外延形成第一硅层; 在该第一层中形成，并且在第一区域上基本上在第二区域分离第二重掺杂P型区域; 在该第二区域的周围形成第三N型区域; 通过外延形成第二硅层; 形成穿过所述第一和第二硅层的深沟槽，穿透到所述衬底中并将所述第二区域与所述第三区域横向分离; 以及执行退火，使得第三区域的掺杂剂与第一区域的掺杂剂连续。

公开(公告)号：US06861684B2

公开(公告)日：2005-03-01

申请号：US10114329

申请日：2002-04-02

Applicant: Thomas Skotnicki ,  Emmanuel Josse

Inventor： Thomas Skotnicki ,  Emmanuel Josse

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/66666 ,  H01L21/2807 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/7827

Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.

Abstract translation: 垂直晶体管在半导体衬底上包括在顶部具有源极和漏极区中的一个的垂直柱5，源极和漏极区中的另一个位于柱的外围的衬底中，栅极介电层 7位于柱的侧面和基板的顶表面上，以及位于栅极介电层上的半导体栅极。 栅极包括具有搁置在栅极电介质层7上的第一区域800的半导体块和面向源极和漏极区域的至少部分的第二区域90，并且通过电介质腔14S，14D与那些源极和漏极区域分离。

公开(公告)号：US20050037599A1

公开(公告)日：2005-02-17

申请号：US10882995

申请日：2004-07-01

Applicant: Aomar Halimaoui ,  Daniel Bensahel

Inventor： Aomar Halimaoui ,  Daniel Bensahel

IPC: H01L21/20 ,  H01L21/324 ,  C30B1/00 ,  H01L21/425

CPC classification number: H01L21/324 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02694 ,  H01L29/7842 ,  Y10S438/96

Abstract: A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes: a) the formation of a layer (2) of silicon or of a silicon/germanium alloy on a layer (1) of a material having a modifiable lattice parameter; and b) the modification of the lattice parameter.

Abstract translation: 一种制造硅或硅/锗合金应变层的工艺包括：a）在具有可修改的材料的层（1）上形成硅层或硅/锗合金层（2） 晶格参数 和b）修改晶格参数。

公开(公告)号：US06853146B2

公开(公告)日：2005-02-08

申请号：US10110449

申请日：2001-08-09

Applicant: Gilles Troussel ,  Céline Mas ,  Eric Benoit

Inventor： Gilles Troussel ,  Céline Mas ,  Eric Benoit

IPC: G09G3/293 ,  G09G3/296 ,  G09G3/10 ,  G09G5/00

CPC classification number: G09G3/293 ,  G09G3/296 ,  G09G2310/0275 ,  G09G2330/025

Abstract: A method for controlling cells of a plasma screen of array type, formed of cells arranged at the intersections of lines and columns, including the step of sequentially applying to each line an activation potential and, during the activation of a line, applying an activation potential to selected columns, in which, while a line is activated, the selected columns are non-simultaneously activated.

Abstract translation: 一种用于控制阵列型等离子体屏的细胞的方法，由排列在线和列交点处的细胞组成，包括依次向每行施加激活电位的步骤，并且在激活线期间施加激活电位 到选定的列，其中当行被激活时，所选择的列不被同时激活。

公开(公告)号：US20050018490A1

公开(公告)日：2005-01-27

申请号：US10867378

申请日：2004-06-14

Applicant: Bruno Leconte ,  Paola Cavaleri ,  Sebastien Zink

Inventor： Bruno Leconte ,  Paola Cavaleri ,  Sebastien Zink

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3418

Abstract: The present invention relates to a method for checking and refreshing a floating-gate transistor in the erased state, comprising the steps of applying a positive erase voltage to a control gate of the floating-gate transistor, and selectively applying a positive erase voltage to the drain of the floating-gate transistor, by means of a programming latch for example. Application to checking and refreshing memory pages in a Flash memory.

Abstract translation: 本发明涉及一种在擦除状态下检查和刷新浮栅晶体管的方法，包括以下步骤：将正擦除电压施加到浮栅晶体管的控制栅极，并选择性地将正擦除电压施加到 通过例如编程锁存器的浮栅晶体管的漏极。 用于检查和刷新闪存中的内存页面的应用程序。

公开(公告)号：US06847094B2

公开(公告)日：2005-01-25

申请号：US10236082

申请日：2002-09-06

Applicant: Thierry Schwartzmann

Inventor： Thierry Schwartzmann

IPC: H01L29/08 ,  H01L29/00

CPC classification number: H01L29/0821

Abstract: The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This intermediary connection region is located under a trench. The manufacturing method enables forming of vertical devices, in particular fast bipolar transistors.

Abstract translation: 与在硅衬底中形成的第一导电类型的深区形成接触。 该接触包括第一导电类型的掺杂硅阱区域和连接在深层和阱之间的中间区域。 该中间连接区位于沟槽下方。 该制造方法能够形成垂直装置，特别是快速双极晶体管。

公开(公告)号：US06839285B2

公开(公告)日：2005-01-04

申请号：US09737170

申请日：2000-12-14

Applicant: Sébastien Zink ,  Bruno Leconte ,  Paola Cavaleri

Inventor： Sébastien Zink ,  Bruno Leconte ,  Paola Cavaleri

IPC: G11C16/10 ,  G06F12/06

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

公开(公告)号：US06838916B2

公开(公告)日：2005-01-04

申请号：US10352776

申请日：2003-01-28

Applicant: Christophe Premont ,  David Chesneau ,  Christophe Bernard

Inventor： Christophe Premont ,  David Chesneau ,  Christophe Bernard

IPC: H02M3/158 ,  H03K3/011 ,  H03K4/502 ,  H03K4/06

CPC classification number: H03K4/502 ,  H02M3/1588 ,  H03K3/011 ,  Y02B70/1466

Abstract: A ramp capacitor CAP1 has a first terminal connected to a power supply voltage VBAT. A generator circuit is connected to a second terminal of the ramp capacitor and adapted to generate a voltage ramp at the terminals of the ramp capacitor. The generator circuit includes a constant current source SCC connected to the second terminal B12 of the ramp capacitor CAP1 and auxiliary circuit MAX adapted in the presence of a transient variation of the power supply voltage to determine the transient current flowing in the ramp capacitor and generated by the transient variation. Responsive thereto, delivery is made to the second terminal B12 of the ramp capacitor CAP1 of a charging current equal to the algebraic sum of the constant current delivered by the constant current source and an auxiliary current equal and opposite to the transient current.

Abstract translation: 斜坡电容器CAP1具有连接到电源电压VBAT的第一端子。 发电机电路连接到斜坡电容器的第二端子，适于在斜坡电容器的端子处产生电压斜坡。 发电机电路包括连接到斜坡电容器CAP1的第二端子B12的恒流源SCC和辅助电路MAX，其适应于存在电源电压的瞬时变化，以确定在斜坡电容器中流动的瞬态电流并由 瞬态变化。 响应于此，向斜坡电容器CAP1的第二端子B12输送等于由恒流源输送的恒定电流的代数和与瞬态电流相等且相反的辅助电流的充电电流。